1 //===- MipsInstrFPU.td - Mips FPU Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisSameAs<0, 2>, SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<0>,
31 def SDT_MipsFPSelectCC : SDTypeProfile<1, 4, [SDTCisInt<1>, SDTCisInt<4>,
32 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
33 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
35 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp>;
36 def MipsFPSelectCC : SDNode<"MipsISD::FPSelectCC", SDT_MipsFPSelectCC>;
38 // Operand for printing out a condition code.
39 let PrintMethod = "printFCCOperand" in
40 def condcode : Operand<i32>;
42 //===----------------------------------------------------------------------===//
43 // Feature predicates.
44 //===----------------------------------------------------------------------===//
46 def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
47 def In64BitMode : Predicate<"Subtarget.isFP64bit()">;
48 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
49 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
51 //===----------------------------------------------------------------------===//
52 // Instruction Class Templates
54 // A set of multiclasses is used to address this in one shot.
55 // SO32 - single precision only, uses all 32 32-bit fp registers
56 // require FGR32 Register Class and IsSingleFloat
57 // AS32 - 16 even fp registers are used for single precision
58 // require AFGR32 Register Class and In32BitMode
59 // S64 - 32 64 bit registers are used to hold 32-bit single precision values.
60 // require FGR64 Register Class and In64BitMode
61 // D32 - 16 even fp registers are used for double precision
62 // require AFGR64 Register Class and In32BitMode
63 // D64 - 32 64 bit registers are used to hold 64-bit double precision values.
64 // require FGR64 Register Class and In64BitMode
66 // Only SO32, AS32 and D32 are supported right now.
68 //===----------------------------------------------------------------------===//
70 multiclass FFR1_1<bits<6> funct, string asmstr>
72 def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
73 !strconcat(asmstr, ".s $fd, $fs"), []>, Requires<[IsSingleFloat]>;
75 def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd), (ins AFGR32:$fs),
76 !strconcat(asmstr, ".s $fd, $fs"), []>, Requires<[In32BitMode]>;
78 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
79 !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
82 multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
84 def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
85 !strconcat(asmstr, ".s $fd, $fs"),
86 [(set FGR32:$fd, (FOp FGR32:$fs))]>, Requires<[IsSingleFloat]>;
88 def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd), (ins AFGR32:$fs),
89 !strconcat(asmstr, ".s $fd, $fs"),
90 [(set AFGR32:$fd, (FOp AFGR32:$fs))]>, Requires<[In32BitMode]>;
92 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
93 !strconcat(asmstr, ".d $fd, $fs"),
94 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
97 class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
98 RegisterClass RcDst, string asmstr>:
99 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
100 !strconcat(asmstr, " $fd, $fs"), []>;
103 multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
104 def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
105 (ins FGR32:$fs, FGR32:$ft),
106 !strconcat(asmstr, ".s $fd, $fs, $ft"),
107 [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>,
108 Requires<[IsSingleFloat]>;
110 def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd),
111 (ins AFGR32:$fs, AFGR32:$ft),
112 !strconcat(asmstr, ".s $fd, $fs, $ft"),
113 [(set AFGR32:$fd, (FOp AFGR32:$fs, AFGR32:$ft))]>,
114 Requires<[In32BitMode]>;
116 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
117 (ins AFGR64:$fs, AFGR64:$ft),
118 !strconcat(asmstr, ".d $fd, $fs, $ft"),
119 [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
120 Requires<[In32BitMode]>;
123 //===----------------------------------------------------------------------===//
124 // Floating Point Instructions
125 //===----------------------------------------------------------------------===//
128 defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
129 defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
130 defm ROUND_W : FFR1_1<0b001100, "round.w">;
131 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
132 defm CVTW : FFR1_1<0b100100, "cvt.w">;
133 defm FMOV : FFR1_1<0b000110, "mov">;
135 defm FABS : FFR1_2<0b000101, "abs", fabs>;
136 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
137 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
139 let Predicates = [IsNotSingleFloat] in {
140 /// Ceil to long signed integer
141 def CEIL_LS : FFR1_3<0b001010, 0x0, AFGR32, AFGR32, "ceil.l">;
142 def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
144 /// Round to long signed integer
145 def ROUND_LS : FFR1_3<0b001000, 0x0, AFGR32, AFGR32, "round.l">;
146 def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
148 /// Floor to long signed integer
149 def FLOOR_LS : FFR1_3<0b001011, 0x0, AFGR32, AFGR32, "floor.l">;
150 def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
152 /// Trunc to long signed integer
153 def TRUNC_LS : FFR1_3<0b001001, 0x0, AFGR32, AFGR32, "trunc.l">;
154 def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
156 /// Convert to long signed integer
157 def CVTL_S : FFR1_3<0b100101, 0x0, AFGR32, AFGR32, "cvt.l">;
158 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
160 /// Convert to Double Precison
161 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
162 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
163 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
165 /// Convert to Single Precison
166 def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
167 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
170 /// Convert to Single Precison
171 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">,
172 Requires<[IsSingleFloat]>;
175 // The odd-numbered registers are only referenced when doing loads,
176 // stores, and moves between floating-point and integer registers.
177 // When defining instructions, we reference all 32-bit registers,
178 // regardless of register aliasing.
180 /// Move Control Registers From/To CPU Registers
181 ///def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins FGR32:$fs),
182 /// "cfc1 $rt, $fs", []>;
184 ///def CTC1 : FFR<0x11, 0x0, 0x6, (outs CPURegs:$rt), (ins FGR32:$fs),
185 /// "ctc1 $rt, $fs", []>;
187 ///def CFC1A : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins AFGR32:$fs),
188 /// "cfc1 $rt, $fs", []>;
190 ///def CTC1A : FFR<0x11, 0x0, 0x6, (outs CPURegs:$rt), (ins AFGR32:$fs),
191 /// "ctc1 $rt, $fs", []>;
193 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
194 "mfc1 $rt, $fs", []>;
196 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
197 "mtc1 $rt, $fs", []>;
199 def MFC1A : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins AFGR32:$fs),
200 "mfc1 $rt, $fs", []>;
202 def MTC1A : FFR<0x11, 0x00, 0x04, (outs AFGR32:$fs), (ins CPURegs:$rt),
203 "mtc1 $rt, $fs", []>;
206 /// Floating Point Memory Instructions
207 let Predicates = [IsNotSingleFloat] in {
208 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
209 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
211 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
212 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
215 // LWC1 and SWC1 can always be emited with odd registers.
216 def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
217 [(set FGR32:$ft, (load addr:$addr))]>;
218 def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
219 [(store FGR32:$ft, addr:$addr)]>;
221 def LWC1A : FFI<0b110001, (outs AFGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
222 [(set AFGR32:$ft, (load addr:$addr))]>;
223 def SWC1A : FFI<0b111001, (outs), (ins AFGR32:$ft, mem:$addr),
224 "swc1 $ft, $addr", [(store AFGR32:$ft, addr:$addr)]>;
226 /// Floating-point Aritmetic
227 defm FADD : FFR1_4<0x10, "add", fadd>;
228 defm FDIV : FFR1_4<0x03, "div", fdiv>;
229 defm FMUL : FFR1_4<0x02, "mul", fmul>;
230 defm FSUB : FFR1_4<0x01, "sub", fsub>;
232 //===----------------------------------------------------------------------===//
233 // Floating Point Branch Codes
234 //===----------------------------------------------------------------------===//
235 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
236 // They must be kept in synch.
237 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
238 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
239 def MIPS_BRANCH_FL : PatLeaf<(i32 2)>;
240 def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
242 /// Floating Point Branch of False/True (Likely)
243 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in {
244 class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
245 (ins brtarget:$dst), !strconcat(asmstr, " $dst"),
246 [(MipsFPBrcond op, bb:$dst, FCR31)]>;
248 def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
249 def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
250 def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
251 def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
253 //===----------------------------------------------------------------------===//
254 // Floating Point Flag Conditions
255 //===----------------------------------------------------------------------===//
256 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
257 // They must be kept in synch.
258 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
259 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
260 def MIPS_FCOND_EQ : PatLeaf<(i32 2)>;
261 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
262 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
263 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
264 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
265 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
266 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
267 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
268 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
269 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
270 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
271 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
272 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
273 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
275 /// Floating Point Compare
276 let hasDelaySlot = 1, Defs=[FCR31] in {
277 def FCMP_SO32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
278 "c.$cc.s $fs, $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc),
279 (implicit FCR31)]>, Requires<[IsSingleFloat]>;
281 def FCMP_AS32 : FCC<0x0, (outs), (ins AFGR32:$fs, AFGR32:$ft, condcode:$cc),
282 "c.$cc.s $fs, $ft", [(MipsFPCmp AFGR32:$fs, AFGR32:$ft, imm:$cc),
283 (implicit FCR31)]>, Requires<[In32BitMode]>;
285 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
286 "c.$cc.d $fs, $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc),
287 (implicit FCR31)]>, Requires<[In32BitMode]>;
290 //===----------------------------------------------------------------------===//
291 // Floating Point Pseudo-Instructions
292 //===----------------------------------------------------------------------===//
294 // For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
295 // condiciton code to enable easy handling by the Custom Inserter.
296 let usesCustomDAGSchedInserter = 1, Uses=[FCR31] in {
297 class PseudoFPSelCC<RegisterClass RC, string asmstr> :
298 MipsPseudo<(outs RC:$dst),
299 (ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
300 [(set RC:$dst, (MipsFPSelectCC CPURegs:$CmpRes, RC:$T, RC:$F,
304 // The values to be selected are fp but the condition test is with integers.
305 def Select_CC_SO32 : PseudoSelCC<FGR32, "# MipsSelect_CC_SO32_f32">,
306 Requires<[IsSingleFloat]>;
307 def Select_CC_AS32 : PseudoSelCC<AFGR32, "# MipsSelect_CC_AS32_f32">,
308 Requires<[In32BitMode]>;
309 def Select_CC_D32 : PseudoSelCC<AFGR64, "# MipsSelect_CC_D32_f32">,
310 Requires<[In32BitMode]>;
312 // The values to be selected are int but the condition test is done with fp.
313 def Select_FCC : PseudoFPSelCC<CPURegs, "# MipsSelect_FCC">;
315 // The values to be selected and the condition test is done with fp.
316 def Select_FCC_SO32 : PseudoFPSelCC<FGR32, "# MipsSelect_FCC_SO32_f32">,
317 Requires<[IsSingleFloat]>;
318 def Select_FCC_AS32 : PseudoFPSelCC<AFGR32, "# MipsSelect_FCC_AS32_f32">,
319 Requires<[In32BitMode]>;
320 def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">,
321 Requires<[In32BitMode]>;
324 //===----------------------------------------------------------------------===//
325 // Floating Point Patterns
326 //===----------------------------------------------------------------------===//
327 def fpimm0 : PatLeaf<(fpimm), [{
328 return N->isExactlyValue(+0.0);
331 def : Pat<(f32 fpimm0), (MTC1 ZERO)>, Requires<[IsSingleFloat]>;
332 def : Pat<(f32 fpimm0), (MTC1A ZERO)>, Requires<[In32BitMode]>;
334 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
335 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
337 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_SO32 FGR32:$src))>;
338 def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1A (TRUNC_W_AS32 AFGR32:$src))>;
340 def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
341 def : Pat<(i32 (bitconvert AFGR32:$src)), (MFC1A AFGR32:$src)>;
343 def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>,
344 Requires<[IsSingleFloat]>;
345 def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1A CPURegs:$src)>,
346 Requires<[In32BitMode]>;