1 //===- MipsInstrFPU.td - Mips FPU Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisSameAs<0, 2>, SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<0>,
31 def SDT_MipsFPSelectCC : SDTypeProfile<1, 4, [SDTCisInt<1>, SDTCisInt<4>,
32 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
34 def MipsFPRound : SDNode<"MipsISD::FPRound", SDTFPRoundOp, [SDNPOptInFlag]>;
35 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
37 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp>;
38 def MipsFPSelectCC : SDNode<"MipsISD::FPSelectCC", SDT_MipsFPSelectCC>;
40 // Operand for printing out a condition code.
41 let PrintMethod = "printFCCOperand" in
42 def condcode : Operand<i32>;
44 //===----------------------------------------------------------------------===//
45 // Feature predicates.
46 //===----------------------------------------------------------------------===//
48 def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
49 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
50 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
51 def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
53 //===----------------------------------------------------------------------===//
54 // Instruction Class Templates
56 // A set of multiclasses is used to address the register usage.
58 // S32 - single precision in 16 32bit even fp registers
59 // single precision in 32 32bit fp registers in SingleOnly mode
60 // S64 - single precision in 32 64bit fp registers (In64BitMode)
61 // D32 - double precision in 16 32bit even fp registers
62 // D64 - double precision in 32 64bit fp registers (In64BitMode)
64 // Only S32 and D32 are supported right now.
65 //===----------------------------------------------------------------------===//
67 multiclass FFR1_1<bits<6> funct, string asmstr>
69 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
70 !strconcat(asmstr, ".s $fd, $fs"), []>;
72 def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs),
73 !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
76 multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
78 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
79 !strconcat(asmstr, ".s $fd, $fs"),
80 [(set FGR32:$fd, (FOp FGR32:$fs))]>;
82 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
83 !strconcat(asmstr, ".d $fd, $fs"),
84 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
87 class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
88 RegisterClass RcDst, string asmstr>:
89 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
90 !strconcat(asmstr, " $fd, $fs"), []>;
93 multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
94 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
95 (ins FGR32:$fs, FGR32:$ft),
96 !strconcat(asmstr, ".s $fd, $fs, $ft"),
97 [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
99 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
100 (ins AFGR64:$fs, AFGR64:$ft),
101 !strconcat(asmstr, ".d $fd, $fs, $ft"),
102 [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
103 Requires<[In32BitMode]>;
106 //===----------------------------------------------------------------------===//
107 // Floating Point Instructions
108 //===----------------------------------------------------------------------===//
111 defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
112 defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
113 defm ROUND_W : FFR1_1<0b001100, "round.w">;
114 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
115 defm CVTW : FFR1_1<0b100100, "cvt.w">;
116 defm FMOV : FFR1_1<0b000110, "mov">;
118 defm FABS : FFR1_2<0b000101, "abs", fabs>;
119 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
120 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
122 /// Convert to Single Precison
123 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
125 let Predicates = [IsNotSingleFloat] in {
126 /// Ceil to long signed integer
127 def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
128 def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
130 /// Round to long signed integer
131 def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
132 def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
134 /// Floor to long signed integer
135 def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
136 def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
138 /// Trunc to long signed integer
139 def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
140 def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
142 /// Convert to long signed integer
143 def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
144 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
146 /// Convert to Double Precison
147 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
148 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
149 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
151 /// Convert to Single Precison
152 def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
153 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
157 // The odd-numbered registers are only referenced when doing loads,
158 // stores, and moves between floating-point and integer registers.
159 // When defining instructions, we reference all 32-bit registers,
160 // regardless of register aliasing.
162 /// Move Control Registers From/To CPU Registers
163 def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
164 "cfc1 $rt, $fs", []>;
166 def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
167 "ctc1 $fs, $rt", []>;
169 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
170 "mfc1 $rt, $fs", []>;
172 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
173 "mtc1 $rt, $fs", []>;
176 /// Floating Point Memory Instructions
177 let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
178 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
179 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
181 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
182 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
185 // LWC1 and SWC1 can always be emited with odd registers.
186 def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
187 [(set FGR32:$ft, (load addr:$addr))]>;
188 def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
189 [(store FGR32:$ft, addr:$addr)]>;
191 /// Floating-point Aritmetic
192 defm FADD : FFR1_4<0x10, "add", fadd>;
193 defm FDIV : FFR1_4<0x03, "div", fdiv>;
194 defm FMUL : FFR1_4<0x02, "mul", fmul>;
195 defm FSUB : FFR1_4<0x01, "sub", fsub>;
197 //===----------------------------------------------------------------------===//
198 // Floating Point Branch Codes
199 //===----------------------------------------------------------------------===//
200 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
201 // They must be kept in synch.
202 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
203 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
204 def MIPS_BRANCH_FL : PatLeaf<(i32 2)>;
205 def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
207 /// Floating Point Branch of False/True (Likely)
208 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in {
209 class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
210 (ins brtarget:$dst), !strconcat(asmstr, " $dst"),
211 [(MipsFPBrcond op, bb:$dst, FCR31)]>;
213 def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
214 def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
215 def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
216 def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
218 //===----------------------------------------------------------------------===//
219 // Floating Point Flag Conditions
220 //===----------------------------------------------------------------------===//
221 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
222 // They must be kept in synch.
223 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
224 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
225 def MIPS_FCOND_EQ : PatLeaf<(i32 2)>;
226 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
227 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
228 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
229 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
230 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
231 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
232 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
233 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
234 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
235 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
236 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
237 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
238 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
240 /// Floating Point Compare
241 let hasDelaySlot = 1, Defs=[FCR31] in {
242 def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
243 "c.$cc.s $fs, $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc),
246 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
247 "c.$cc.d $fs, $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc),
248 (implicit FCR31)]>, Requires<[In32BitMode]>;
251 //===----------------------------------------------------------------------===//
252 // Floating Point Pseudo-Instructions
253 //===----------------------------------------------------------------------===//
255 // For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
256 // condiciton code to enable easy handling by the Custom Inserter.
257 let usesCustomInserter = 1, Uses=[FCR31] in {
258 class PseudoFPSelCC<RegisterClass RC, string asmstr> :
259 MipsPseudo<(outs RC:$dst),
260 (ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
261 [(set RC:$dst, (MipsFPSelectCC CPURegs:$CmpRes, RC:$T, RC:$F,
265 // The values to be selected are fp but the condition test is with integers.
266 def Select_CC_S32 : PseudoSelCC<FGR32, "# MipsSelect_CC_S32_f32">;
267 def Select_CC_D32 : PseudoSelCC<AFGR64, "# MipsSelect_CC_D32_f32">,
268 Requires<[In32BitMode]>;
270 // The values to be selected are int but the condition test is done with fp.
271 def Select_FCC : PseudoFPSelCC<CPURegs, "# MipsSelect_FCC">;
273 // The values to be selected and the condition test is done with fp.
274 def Select_FCC_S32 : PseudoFPSelCC<FGR32, "# MipsSelect_FCC_S32_f32">;
275 def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">,
276 Requires<[In32BitMode]>;
278 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
279 "# MOVCCRToCCR", []>;
281 //===----------------------------------------------------------------------===//
282 // Floating Point Patterns
283 //===----------------------------------------------------------------------===//
284 def fpimm0 : PatLeaf<(fpimm), [{
285 return N->isExactlyValue(+0.0);
288 def fpimm0neg : PatLeaf<(fpimm), [{
289 return N->isExactlyValue(-0.0);
292 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
293 def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
295 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
296 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
298 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
300 def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
301 def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
303 let Predicates = [In32BitMode] in {
304 def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
305 def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
308 // MipsFPRound is only emitted for MipsI targets.
309 def : Pat<(f32 (MipsFPRound AFGR64:$src)), (CVTW_D32 AFGR64:$src)>;