1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
34 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
37 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
41 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
42 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
44 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
45 [SDNPHasChain, SDNPOptInGlue]>;
46 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
47 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
48 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
49 SDT_MipsExtractElementF64>;
51 // Operand for printing out a condition code.
52 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
53 def condcode : Operand<i32>;
55 //===----------------------------------------------------------------------===//
56 // Feature predicates.
57 //===----------------------------------------------------------------------===//
59 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
60 AssemblerPredicate<"FeatureFP64Bit">;
61 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
62 AssemblerPredicate<"!FeatureFP64Bit">;
63 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"FeatureSingleFloat">;
65 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
66 AssemblerPredicate<"!FeatureSingleFloat">;
68 // FP immediate patterns.
69 def fpimm0 : PatLeaf<(fpimm), [{
70 return N->isExactlyValue(+0.0);
73 def fpimm0neg : PatLeaf<(fpimm), [{
74 return N->isExactlyValue(-0.0);
77 //===----------------------------------------------------------------------===//
78 // Instruction Class Templates
80 // A set of multiclasses is used to address the register usage.
82 // S32 - single precision in 16 32bit even fp registers
83 // single precision in 32 32bit fp registers in SingleOnly mode
84 // S64 - single precision in 32 64bit fp registers (In64BitMode)
85 // D32 - double precision in 16 32bit even fp registers
86 // D64 - double precision in 32 64bit fp registers (In64BitMode)
88 // Only S32 and D32 are supported right now.
89 //===----------------------------------------------------------------------===//
91 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
92 SDPatternOperator OpNode= null_frag> :
93 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
94 !strconcat(opstr, "\t$fd, $fs, $ft"),
95 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
96 let isCommutable = IsComm;
99 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
100 SDPatternOperator OpNode = null_frag> {
101 def _D32 : ADDS_FT<opstr, AFGR64RegsOpnd, Itin, IsComm, OpNode>,
102 Requires<[NotFP64bit, HasStdEnc]>;
103 def _D64 : ADDS_FT<opstr, FGR64RegsOpnd, Itin, IsComm, OpNode>,
104 Requires<[IsFP64bit, HasStdEnc]> {
105 string DecoderNamespace = "Mips64";
109 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
110 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
111 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
112 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
115 multiclass ABSS_M<string opstr, InstrItinClass Itin,
116 SDPatternOperator OpNode= null_frag> {
117 def _D32 : ABSS_FT<opstr, AFGR64RegsOpnd, AFGR64RegsOpnd, Itin, OpNode>,
118 Requires<[NotFP64bit, HasStdEnc]>;
119 def _D64 : ABSS_FT<opstr, FGR64RegsOpnd, FGR64RegsOpnd, Itin, OpNode>,
120 Requires<[IsFP64bit, HasStdEnc]> {
121 string DecoderNamespace = "Mips64";
125 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
126 def _D32 : ABSS_FT<opstr, FGR32RegsOpnd, AFGR64RegsOpnd, Itin>,
127 Requires<[NotFP64bit, HasStdEnc]>;
128 def _D64 : ABSS_FT<opstr, FGR32RegsOpnd, FGR64RegsOpnd, Itin>,
129 Requires<[IsFP64bit, HasStdEnc]> {
130 let DecoderNamespace = "Mips64";
134 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
135 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
136 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
137 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
139 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
140 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
141 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
142 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
144 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
145 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
146 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
147 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
148 let DecoderMethod = "DecodeFMem";
152 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
153 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
154 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
155 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
156 let DecoderMethod = "DecodeFMem";
160 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
161 SDPatternOperator OpNode = null_frag> :
162 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
163 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
164 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
166 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
167 SDPatternOperator OpNode = null_frag> :
168 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
169 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
170 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
173 class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
174 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
175 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
176 !strconcat(opstr, "\t$fd, ${index}(${base})"),
177 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
178 let AddedComplexity = 20;
181 class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
182 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
183 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
184 !strconcat(opstr, "\t$fs, ${index}(${base})"),
185 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
186 let AddedComplexity = 20;
189 class BC1F_FT<string opstr, InstrItinClass Itin,
190 SDPatternOperator Op = null_frag> :
191 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
192 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
194 let isTerminator = 1;
195 let hasDelaySlot = 1;
200 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
201 SDPatternOperator OpNode = null_frag> :
202 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
203 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
204 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
206 let isCodeGenOnly = 1;
209 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> :
210 InstSE<(outs), (ins RC:$fs, RC:$ft),
211 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp,
214 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> {
215 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>;
216 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>;
217 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>;
218 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>;
219 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>;
220 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>;
221 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>;
222 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>;
223 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>;
224 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>;
225 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>;
226 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>;
227 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>;
228 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>;
229 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>;
230 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>;
233 defm S : C_COND_M<"s", FGR32RegsOpnd, 16>;
234 defm D32 : C_COND_M<"d", AFGR64RegsOpnd, 17>,
235 Requires<[NotFP64bit, HasStdEnc]>;
236 let DecoderNamespace = "Mips64" in
237 defm D64 : C_COND_M<"d", FGR64RegsOpnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
239 //===----------------------------------------------------------------------===//
240 // Floating Point Instructions
241 //===----------------------------------------------------------------------===//
242 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
244 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
246 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
248 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
250 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
253 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
254 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
255 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
256 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
257 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
259 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
260 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
262 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
264 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
266 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
268 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
270 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
272 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
274 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
278 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
280 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
282 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
285 let Predicates = [NotFP64bit, HasStdEnc] in {
286 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, AFGR64RegsOpnd, IIFcvt>,
288 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
290 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
294 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
295 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
297 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
299 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
301 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
303 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
307 let isPseudo = 1, isCodeGenOnly = 1 in {
308 def PseudoCVT_S_W : ABSS_FT<"", FGR32RegsOpnd, CPURegsOpnd, IIFcvt>;
309 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64RegsOpnd, CPURegsOpnd, IIFcvt>;
310 def PseudoCVT_S_L : ABSS_FT<"", FGR64RegsOpnd, CPU64RegsOpnd, IIFcvt>;
311 def PseudoCVT_D64_W : ABSS_FT<"", FGR64RegsOpnd, CPURegsOpnd, IIFcvt>;
312 def PseudoCVT_D64_L : ABSS_FT<"", FGR64RegsOpnd, CPU64RegsOpnd, IIFcvt>;
315 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
316 def FABS_S : ABSS_FT<"abs.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fabs>,
318 def FNEG_S : ABSS_FT<"neg.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fneg>,
320 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
321 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
324 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFsqrtSingle,
325 fsqrt>, ABSS_FM<0x4, 16>;
326 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
328 // The odd-numbered registers are only referenced when doing loads,
329 // stores, and moves between floating-point and integer registers.
330 // When defining instructions, we reference all 32-bit registers,
331 // regardless of register aliasing.
333 /// Move Control Registers From/To CPU Registers
334 def CFC1 : MFC1_FT<"cfc1", CPURegsOpnd, CCROpnd, IIFmove>, MFC1_FM<2>;
335 def CTC1 : MTC1_FT<"ctc1", CCROpnd, CPURegsOpnd, IIFmove>, MFC1_FM<6>;
336 def MFC1 : MFC1_FT<"mfc1", CPURegsOpnd, FGR32RegsOpnd, IIFmoveC1, bitconvert>,
338 def MTC1 : MTC1_FT<"mtc1", FGR32RegsOpnd, CPURegsOpnd, IIFmoveC1, bitconvert>,
340 def DMFC1 : MFC1_FT<"dmfc1", CPU64RegsOpnd, FGR64RegsOpnd, IIFmoveC1,
341 bitconvert>, MFC1_FM<1>;
342 def DMTC1 : MTC1_FT<"dmtc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFmoveC1,
343 bitconvert>, MFC1_FM<5>;
345 def FMOV_S : ABSS_FT<"mov.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFmove>,
347 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64RegsOpnd, AFGR64RegsOpnd, IIFmove>,
348 ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>;
349 def FMOV_D64 : ABSS_FT<"mov.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFmove>,
350 ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> {
351 let DecoderNamespace = "Mips64";
354 /// Floating Point Memory Instructions
355 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
356 def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem64, load>,
358 def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem64, store>,
360 def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem64, load>,
362 let isCodeGenOnly =1;
364 def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem64, store>,
366 let isCodeGenOnly =1;
370 let Predicates = [NotN64, HasStdEnc] in {
371 def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem, load>, LW_FM<0x31>;
372 def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem, store>, LW_FM<0x39>;
375 let Predicates = [NotN64, HasMips64, HasStdEnc],
376 DecoderNamespace = "Mips64" in {
377 def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem, load>, LW_FM<0x35>;
378 def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem, store>, LW_FM<0x3d>;
381 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
382 let isPseudo = 1, isCodeGenOnly = 1 in {
383 def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IIFLoad, mem, load>;
384 def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIFStore, mem, store>;
386 def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IIFLoad, mem>, LW_FM<0x35>;
387 def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIFStore, mem>, LW_FM<0x3d>;
390 // Indexed loads and stores.
391 let Predicates = [HasFPIdx, HasStdEnc] in {
392 def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IIFLoad, load>,
394 def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIFStore, store>,
398 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
399 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>,
401 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore, store>,
405 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
406 def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>,
408 def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore, store>,
413 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
414 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFLoad, load>,
416 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFLoad,
418 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFStore,
420 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFStore,
424 // Load/store doubleword indexed unaligned.
425 let Predicates = [NotMips64, HasStdEnc] in {
426 def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad>,
428 def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore>,
432 let Predicates = [HasMips64, HasStdEnc],
433 DecoderNamespace="Mips64" in {
434 def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad>,
436 def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore>,
440 /// Floating-point Aritmetic
441 def FADD_S : ADDS_FT<"add.s", FGR32RegsOpnd, IIFadd, 1, fadd>,
443 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
444 def FDIV_S : ADDS_FT<"div.s", FGR32RegsOpnd, IIFdivSingle, 0, fdiv>,
446 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
447 def FMUL_S : ADDS_FT<"mul.s", FGR32RegsOpnd, IIFmulSingle, 1, fmul>,
449 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
450 def FSUB_S : ADDS_FT<"sub.s", FGR32RegsOpnd, IIFadd, 0, fsub>,
452 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
454 let Predicates = [HasMips32r2, HasStdEnc] in {
455 def MADD_S : MADDS_FT<"madd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
457 def MSUB_S : MADDS_FT<"msub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
461 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
462 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
464 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
468 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
469 def MADD_D32 : MADDS_FT<"madd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
471 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
475 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
476 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
478 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
482 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
483 def MADD_D64 : MADDS_FT<"madd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
485 def MSUB_D64 : MADDS_FT<"msub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
489 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
491 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
493 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
497 //===----------------------------------------------------------------------===//
498 // Floating Point Branch Codes
499 //===----------------------------------------------------------------------===//
500 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
501 // They must be kept in synch.
502 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
503 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
505 let DecoderMethod = "DecodeBC1" in {
506 def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
507 def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
509 //===----------------------------------------------------------------------===//
510 // Floating Point Flag Conditions
511 //===----------------------------------------------------------------------===//
512 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
513 // They must be kept in synch.
514 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
515 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
516 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
517 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
518 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
519 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
520 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
521 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
522 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
523 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
524 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
525 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
526 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
527 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
528 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
529 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
531 /// Floating Point Compare
532 def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
533 def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
534 Requires<[NotFP64bit, HasStdEnc]>;
535 let DecoderNamespace = "Mips64" in
536 def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
537 Requires<[IsFP64bit, HasStdEnc]>;
539 //===----------------------------------------------------------------------===//
540 // Floating Point Pseudo-Instructions
541 //===----------------------------------------------------------------------===//
543 // This pseudo instr gets expanded into 2 mtc1 instrs after register
546 PseudoSE<(outs AFGR64RegsOpnd:$dst),
547 (ins CPURegsOpnd:$lo, CPURegsOpnd:$hi),
548 [(set AFGR64RegsOpnd:$dst,
549 (MipsBuildPairF64 CPURegsOpnd:$lo, CPURegsOpnd:$hi))]>;
551 // This pseudo instr gets expanded into 2 mfc1 instrs after register
553 // if n is 0, lower part of src is extracted.
554 // if n is 1, higher part of src is extracted.
555 def ExtractElementF64 :
556 PseudoSE<(outs CPURegsOpnd:$dst), (ins AFGR64RegsOpnd:$src, i32imm:$n),
557 [(set CPURegsOpnd:$dst,
558 (MipsExtractElementF64 AFGR64RegsOpnd:$src, imm:$n))]>;
560 //===----------------------------------------------------------------------===//
561 // Floating Point Patterns
562 //===----------------------------------------------------------------------===//
563 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
564 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
566 def : MipsPat<(f32 (sint_to_fp CPURegsOpnd:$src)),
567 (PseudoCVT_S_W CPURegsOpnd:$src)>;
568 def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
569 (TRUNC_W_S FGR32RegsOpnd:$src)>;
571 let Predicates = [NotFP64bit, HasStdEnc] in {
572 def : MipsPat<(f64 (sint_to_fp CPURegsOpnd:$src)),
573 (PseudoCVT_D32_W CPURegsOpnd:$src)>;
574 def : MipsPat<(MipsTruncIntFP AFGR64RegsOpnd:$src),
575 (TRUNC_W_D32 AFGR64RegsOpnd:$src)>;
576 def : MipsPat<(f32 (fround AFGR64RegsOpnd:$src)),
577 (CVT_S_D32 AFGR64RegsOpnd:$src)>;
578 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
579 (CVT_D32_S FGR32RegsOpnd:$src)>;
582 let Predicates = [IsFP64bit, HasStdEnc] in {
583 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
584 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
586 def : MipsPat<(f64 (sint_to_fp CPURegsOpnd:$src)),
587 (PseudoCVT_D64_W CPURegsOpnd:$src)>;
588 def : MipsPat<(f32 (sint_to_fp CPU64RegsOpnd:$src)),
589 (EXTRACT_SUBREG (PseudoCVT_S_L CPU64RegsOpnd:$src), sub_32)>;
590 def : MipsPat<(f64 (sint_to_fp CPU64RegsOpnd:$src)),
591 (PseudoCVT_D64_L CPU64RegsOpnd:$src)>;
593 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
594 (TRUNC_W_D64 FGR64RegsOpnd:$src)>;
595 def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
596 (TRUNC_L_S FGR32RegsOpnd:$src)>;
597 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
598 (TRUNC_L_D64 FGR64RegsOpnd:$src)>;
600 def : MipsPat<(f32 (fround FGR64RegsOpnd:$src)),
601 (CVT_S_D64 FGR64RegsOpnd:$src)>;
602 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
603 (CVT_D64_S FGR32RegsOpnd:$src)>;
606 // Patterns for loads/stores with a reg+imm operand.
607 let AddedComplexity = 40 in {
608 let Predicates = [IsN64, HasStdEnc] in {
609 def : LoadRegImmPat<LWC1_P8, f32, load>;
610 def : StoreRegImmPat<SWC1_P8, f32>;
611 def : LoadRegImmPat<LDC164_P8, f64, load>;
612 def : StoreRegImmPat<SDC164_P8, f64>;
615 let Predicates = [NotN64, HasStdEnc] in {
616 def : LoadRegImmPat<LWC1, f32, load>;
617 def : StoreRegImmPat<SWC1, f32>;
620 let Predicates = [NotN64, HasMips64, HasStdEnc] in {
621 def : LoadRegImmPat<LDC164, f64, load>;
622 def : StoreRegImmPat<SDC164, f64>;
625 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
626 def : LoadRegImmPat<PseudoLDC1, f64, load>;
627 def : StoreRegImmPat<PseudoSDC1, f64>;