1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
42 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
43 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
44 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
45 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
46 [SDNPHasChain, SDNPOptInGlue]>;
47 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
48 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
49 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
50 SDT_MipsExtractElementF64>;
52 // Operand for printing out a condition code.
53 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
54 def condcode : Operand<i32>;
56 //===----------------------------------------------------------------------===//
57 // Feature predicates.
58 //===----------------------------------------------------------------------===//
60 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
61 AssemblerPredicate<"FeatureFP64Bit">;
62 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
63 AssemblerPredicate<"!FeatureFP64Bit">;
64 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
65 AssemblerPredicate<"FeatureSingleFloat">;
66 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
67 AssemblerPredicate<"!FeatureSingleFloat">;
69 // FP immediate patterns.
70 def fpimm0 : PatLeaf<(fpimm), [{
71 return N->isExactlyValue(+0.0);
74 def fpimm0neg : PatLeaf<(fpimm), [{
75 return N->isExactlyValue(-0.0);
78 //===----------------------------------------------------------------------===//
79 // Instruction Class Templates
81 // A set of multiclasses is used to address the register usage.
83 // S32 - single precision in 16 32bit even fp registers
84 // single precision in 32 32bit fp registers in SingleOnly mode
85 // S64 - single precision in 32 64bit fp registers (In64BitMode)
86 // D32 - double precision in 16 32bit even fp registers
87 // D64 - double precision in 32 64bit fp registers (In64BitMode)
89 // Only S32 and D32 are supported right now.
90 //===----------------------------------------------------------------------===//
92 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
93 SDPatternOperator OpNode= null_frag> :
94 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
95 !strconcat(opstr, "\t$fd, $fs, $ft"),
96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
97 let isCommutable = IsComm;
100 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
101 SDPatternOperator OpNode = null_frag> {
102 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
103 Requires<[NotFP64bit, HasStdEnc]>;
104 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
106 Requires<[IsFP64bit, HasStdEnc]> {
107 string DecoderNamespace = "Mips64";
111 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
112 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
113 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
114 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
117 multiclass ABSS_M<string opstr, InstrItinClass Itin,
118 SDPatternOperator OpNode= null_frag> {
119 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
120 Requires<[NotFP64bit, HasStdEnc]>;
121 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
122 Requires<[IsFP64bit, HasStdEnc]> {
123 string DecoderNamespace = "Mips64";
127 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
128 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
129 Requires<[NotFP64bit, HasStdEnc]>;
130 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
131 Requires<[IsFP64bit, HasStdEnc]> {
132 let DecoderNamespace = "Mips64";
136 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
137 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
138 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
139 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
141 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
142 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
143 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
144 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
146 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
147 SDPatternOperator OpNode= null_frag> :
148 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
149 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
150 let DecoderMethod = "DecodeFMem";
154 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
155 SDPatternOperator OpNode= null_frag> :
156 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
157 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
158 let DecoderMethod = "DecodeFMem";
162 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
163 SDPatternOperator OpNode = null_frag> :
164 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
165 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
166 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
168 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
169 SDPatternOperator OpNode = null_frag> :
170 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
171 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
172 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
175 class LWXC1_FT<string opstr, RegisterOperand DRC,
176 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
177 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
178 !strconcat(opstr, "\t$fd, ${index}(${base})"),
179 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
181 let AddedComplexity = 20;
184 class SWXC1_FT<string opstr, RegisterOperand DRC,
185 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
186 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
187 !strconcat(opstr, "\t$fs, ${index}(${base})"),
188 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
190 let AddedComplexity = 20;
193 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
194 SDPatternOperator Op = null_frag> :
195 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
196 !strconcat(opstr, "\t$fcc, $offset"),
197 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
200 let isTerminator = 1;
201 let hasDelaySlot = 1;
205 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
206 SDPatternOperator OpNode = null_frag> :
207 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
208 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
209 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
210 !strconcat("c.$cond.", typestr)> {
212 let isCodeGenOnly = 1;
215 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> :
216 InstSE<(outs), (ins RC:$fs, RC:$ft),
217 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp,
220 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> {
221 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>;
222 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>;
223 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>;
224 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>;
225 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>;
226 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>;
227 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>;
228 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>;
229 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>;
230 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>;
231 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>;
232 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>;
233 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>;
234 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>;
235 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>;
236 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>;
239 defm S : C_COND_M<"s", FGR32Opnd, 16>;
240 defm D32 : C_COND_M<"d", AFGR64Opnd, 17>,
241 Requires<[NotFP64bit, HasStdEnc]>;
242 let DecoderNamespace = "Mips64" in
243 defm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
245 //===----------------------------------------------------------------------===//
246 // Floating Point Instructions
247 //===----------------------------------------------------------------------===//
248 def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
250 def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
252 def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
254 def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
256 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>,
259 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
260 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
261 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
262 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
263 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
265 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
266 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
268 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
270 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
272 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
274 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
276 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
278 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
280 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
284 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>,
286 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
288 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>,
291 let Predicates = [NotFP64bit, HasStdEnc] in {
292 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>,
294 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>,
296 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>,
300 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
301 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>,
303 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>,
305 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>,
307 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>,
309 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>,
313 let isPseudo = 1, isCodeGenOnly = 1 in {
314 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>;
315 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>;
316 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
317 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>;
318 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>;
321 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
322 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>,
324 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>,
326 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
327 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
330 def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle,
331 fsqrt>, ABSS_FM<0x4, 16>;
332 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
334 // The odd-numbered registers are only referenced when doing loads,
335 // stores, and moves between floating-point and integer registers.
336 // When defining instructions, we reference all 32-bit registers,
337 // regardless of register aliasing.
339 /// Move Control Registers From/To CPU Registers
340 def CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>;
341 def CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>;
342 def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>,
344 def MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>,
346 def MFHC1 : MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>,
348 def MTHC1 : MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>,
350 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1,
351 bitconvert>, MFC1_FM<1>;
352 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1,
353 bitconvert>, MFC1_FM<5>;
355 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>,
357 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>,
358 ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>;
359 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, IIFmove>,
360 ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> {
361 let DecoderNamespace = "Mips64";
364 /// Floating Point Memory Instructions
365 let Predicates = [HasStdEnc] in {
366 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, IIFLoad, load>, LW_FM<0x31>;
367 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>;
370 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
371 def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>;
372 def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>;
375 let Predicates = [NotFP64bit, HasStdEnc] in {
376 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, IIFLoad, load>, LW_FM<0x35>;
377 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, LW_FM<0x3d>;
380 /// Cop2 Memory Instructions
381 let Predicates = [HasStdEnc] in {
382 def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
383 def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>;
384 def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>;
385 def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>;
388 // Indexed loads and stores.
389 let Predicates = [HasFPIdx, HasStdEnc] in {
390 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>, LWXC1_FM<0>;
391 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, IIFStore, store>,
395 let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips] in {
396 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, IIFLoad, load>, LWXC1_FM<1>;
397 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, IIFStore, store>, SWXC1_FM<9>;
400 let Predicates = [HasFPIdx, IsFP64bit, HasStdEnc],
401 DecoderNamespace="Mips64" in {
402 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, IIFLoad, load>, LWXC1_FM<1>;
403 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, IIFStore, store>, SWXC1_FM<9>;
406 // Load/store doubleword indexed unaligned.
407 let Predicates = [NotFP64bit, HasStdEnc] in {
408 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, IIFLoad>, LWXC1_FM<0x5>;
409 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>, SWXC1_FM<0xd>;
412 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in {
413 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, IIFLoad>, LWXC1_FM<0x5>;
414 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, IIFStore>, SWXC1_FM<0xd>;
417 /// Floating-point Aritmetic
418 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>,
420 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
421 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>,
423 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
424 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>,
426 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
427 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>,
429 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
431 let Predicates = [HasMips32r2, HasStdEnc] in {
432 def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>,
434 def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>,
438 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
439 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>,
441 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>,
445 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
446 def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
448 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
452 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
453 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>,
455 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>,
459 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
460 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>,
462 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>,
466 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
468 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>,
470 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>,
474 //===----------------------------------------------------------------------===//
475 // Floating Point Branch Codes
476 //===----------------------------------------------------------------------===//
477 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
478 // They must be kept in synch.
479 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
480 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
482 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
484 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
487 //===----------------------------------------------------------------------===//
488 // Floating Point Flag Conditions
489 //===----------------------------------------------------------------------===//
490 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
491 // They must be kept in synch.
492 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
493 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
494 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
495 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
496 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
497 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
498 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
499 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
500 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
501 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
502 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
503 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
504 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
505 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
506 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
507 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
509 /// Floating Point Compare
510 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
511 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
512 Requires<[NotFP64bit, HasStdEnc]>;
513 let DecoderNamespace = "Mips64" in
514 def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
515 Requires<[IsFP64bit, HasStdEnc]>;
517 //===----------------------------------------------------------------------===//
518 // Floating Point Pseudo-Instructions
519 //===----------------------------------------------------------------------===//
521 // This pseudo instr gets expanded into 2 mtc1 instrs after register
523 class BuildPairF64Base<RegisterOperand RO> :
524 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
525 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
527 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
528 Requires<[NotFP64bit, HasStdEnc]>;
529 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
530 Requires<[IsFP64bit, HasStdEnc]>;
532 // This pseudo instr gets expanded into 2 mfc1 instrs after register
534 // if n is 0, lower part of src is extracted.
535 // if n is 1, higher part of src is extracted.
536 class ExtractElementF64Base<RegisterOperand RO> :
537 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
538 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
540 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
541 Requires<[NotFP64bit, HasStdEnc]>;
542 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
543 Requires<[IsFP64bit, HasStdEnc]>;
545 //===----------------------------------------------------------------------===//
547 //===----------------------------------------------------------------------===//
548 def : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>;
549 def : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>;
551 //===----------------------------------------------------------------------===//
552 // Floating Point Patterns
553 //===----------------------------------------------------------------------===//
554 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
555 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
557 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
558 (PseudoCVT_S_W GPR32Opnd:$src)>;
559 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
560 (TRUNC_W_S FGR32Opnd:$src)>;
562 let Predicates = [NotFP64bit, HasStdEnc] in {
563 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
564 (PseudoCVT_D32_W GPR32Opnd:$src)>;
565 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
566 (TRUNC_W_D32 AFGR64Opnd:$src)>;
567 def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
568 (CVT_S_D32 AFGR64Opnd:$src)>;
569 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
570 (CVT_D32_S FGR32Opnd:$src)>;
573 let Predicates = [IsFP64bit, HasStdEnc] in {
574 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
575 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
577 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
578 (PseudoCVT_D64_W GPR32Opnd:$src)>;
579 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
580 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>;
581 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
582 (PseudoCVT_D64_L GPR64Opnd:$src)>;
584 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
585 (TRUNC_W_D64 FGR64Opnd:$src)>;
586 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
587 (TRUNC_L_S FGR32Opnd:$src)>;
588 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
589 (TRUNC_L_D64 FGR64Opnd:$src)>;
591 def : MipsPat<(f32 (fround FGR64Opnd:$src)),
592 (CVT_S_D64 FGR64Opnd:$src)>;
593 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
594 (CVT_D64_S FGR32Opnd:$src)>;
597 // Patterns for loads/stores with a reg+imm operand.
598 let AddedComplexity = 40 in {
599 let Predicates = [HasStdEnc] in {
600 def : LoadRegImmPat<LWC1, f32, load>;
601 def : StoreRegImmPat<SWC1, f32>;
604 let Predicates = [IsFP64bit, HasStdEnc] in {
605 def : LoadRegImmPat<LDC164, f64, load>;
606 def : StoreRegImmPat<SDC164, f64>;
609 let Predicates = [NotFP64bit, HasStdEnc] in {
610 def : LoadRegImmPat<LDC1, f64, load>;
611 def : StoreRegImmPat<SDC1, f64>;