1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
58 AssemblerPredicate<"FeatureFP64Bit">;
59 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
60 AssemblerPredicate<"!FeatureFP64Bit">;
61 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
62 AssemblerPredicate<"FeatureSingleFloat">;
63 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"!FeatureSingleFloat">;
66 // FP immediate patterns.
67 def fpimm0 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+0.0);
71 def fpimm0neg : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-0.0);
75 //===----------------------------------------------------------------------===//
76 // Instruction Class Templates
78 // A set of multiclasses is used to address the register usage.
80 // S32 - single precision in 16 32bit even fp registers
81 // single precision in 32 32bit fp registers in SingleOnly mode
82 // S64 - single precision in 32 64bit fp registers (In64BitMode)
83 // D32 - double precision in 16 32bit even fp registers
84 // D64 - double precision in 32 64bit fp registers (In64BitMode)
86 // Only S32 and D32 are supported right now.
87 //===----------------------------------------------------------------------===//
90 let DecoderMethod = "DecodeFMem" in {
91 class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
92 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
93 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))],
97 class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
98 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
99 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
103 class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
104 RegisterClass PRC, SDPatternOperator FOp = null_frag>:
105 FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
106 !strconcat(opstr, "\t$fd, ${index}(${base})"),
107 [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
112 class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
113 RegisterClass PRC, SDPatternOperator FOp= null_frag>:
114 FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
115 !strconcat(opstr, "\t$fs, ${index}(${base})"),
116 [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
120 // Instructions that convert an FP value to 32-bit fixed point.
121 multiclass FFR1_W_M<bits<6> funct, string opstr> {
122 def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
123 def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
124 Requires<[NotFP64bit, HasStdEnc]>;
125 def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
126 Requires<[IsFP64bit, HasStdEnc]> {
127 let DecoderNamespace = "Mips64";
131 // Instructions that convert an FP value to 64-bit fixed point.
132 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in
133 multiclass FFR1_L_M<bits<6> funct, string opstr> {
134 def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
135 def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
138 // FP-to-FP conversion instructions.
139 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
140 def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
141 def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
142 Requires<[NotFP64bit, HasStdEnc]>;
143 def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
144 Requires<[IsFP64bit, HasStdEnc]> {
145 let DecoderNamespace = "Mips64";
149 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
150 let isCommutable = isComm in {
151 def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
152 def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
153 Requires<[NotFP64bit, HasStdEnc]>;
154 def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
155 Requires<[IsFP64bit, HasStdEnc]> {
156 let DecoderNamespace = "Mips64";
161 // FP madd/msub/nmadd/nmsub instruction classes.
162 class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr, string fmtstr,
163 SDNode OpNode, RegisterClass RC> :
164 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
165 !strconcat(opstr, ".", fmtstr, "\t$fd, $fr, $fs, $ft"),
166 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>;
168 class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr, string fmtstr,
169 SDNode OpNode, RegisterClass RC> :
170 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
171 !strconcat(opstr, ".", fmtstr, "\t$fd, $fr, $fs, $ft"),
172 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>;
174 //===----------------------------------------------------------------------===//
175 // Floating Point Instructions
176 //===----------------------------------------------------------------------===//
177 defm ROUND_W : FFR1_W_M<0xc, "round">;
178 defm ROUND_L : FFR1_L_M<0x8, "round">;
179 defm TRUNC_W : FFR1_W_M<0xd, "trunc">;
180 defm TRUNC_L : FFR1_L_M<0x9, "trunc">;
181 defm CEIL_W : FFR1_W_M<0xe, "ceil">;
182 defm CEIL_L : FFR1_L_M<0xa, "ceil">;
183 defm FLOOR_W : FFR1_W_M<0xf, "floor">;
184 defm FLOOR_L : FFR1_L_M<0xb, "floor">;
185 defm CVT_W : FFR1_W_M<0x24, "cvt">, NeverHasSideEffects;
186 //defm CVT_L : FFR1_L_M<0x25, "cvt">;
188 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>, NeverHasSideEffects;
189 def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>, NeverHasSideEffects;
190 def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>, NeverHasSideEffects;
192 let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in {
193 def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
194 def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
195 def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
198 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64",
199 neverHasSideEffects = 1 in {
200 def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
201 def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
202 def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
203 def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>;
204 def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
207 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
208 defm FABS : FFR1P_M<0x5, "abs", fabs>;
209 defm FNEG : FFR1P_M<0x7, "neg", fneg>;
211 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
213 // The odd-numbered registers are only referenced when doing loads,
214 // stores, and moves between floating-point and integer registers.
215 // When defining instructions, we reference all 32-bit registers,
216 // regardless of register aliasing.
218 class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
219 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
225 /// Move Control Registers From/To CPU Registers
226 def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
227 "cfc1\t$rt, $fs", []>;
229 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
230 "ctc1\t$rt, $fs", []>;
232 def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
234 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
236 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
238 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
240 def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs),
242 [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>;
244 def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt),
246 [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>;
248 def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
249 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
250 Requires<[NotFP64bit, HasStdEnc]>;
251 def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
252 Requires<[IsFP64bit, HasStdEnc]> {
253 let DecoderNamespace = "Mips64";
256 /// Floating Point Memory Instructions
257 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
258 def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>;
259 def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>;
260 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
261 let isCodeGenOnly =1;
263 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> {
264 let isCodeGenOnly =1;
268 let Predicates = [NotN64, HasStdEnc] in {
269 def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>;
270 def SWC1 : FPStore<0x39, "swc1", FGR32, mem>;
273 let Predicates = [NotN64, HasMips64, HasStdEnc],
274 DecoderNamespace = "Mips64" in {
275 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
276 def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
279 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
280 def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>;
281 def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>;
284 // Indexed loads and stores.
285 let Predicates = [HasFPIdx, HasStdEnc] in {
286 def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load>;
287 def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store>;
290 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
291 def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load>;
292 def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store>;
295 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
296 def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load>;
297 def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store>;
301 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
302 def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load>;
303 def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load>;
304 def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store>;
305 def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store>;
308 // Load/store doubleword indexed unaligned.
309 let Predicates = [NotMips64, HasStdEnc] in {
310 def LUXC1 : FPIdxLoad<0x5, "luxc1", AFGR64, CPURegs>;
311 def SUXC1 : FPIdxStore<0xd, "suxc1", AFGR64, CPURegs>;
314 let Predicates = [HasMips64, HasStdEnc],
315 DecoderNamespace="Mips64" in {
316 def LUXC164 : FPIdxLoad<0x5, "luxc1", FGR64, CPURegs>;
317 def SUXC164 : FPIdxStore<0xd, "suxc1", FGR64, CPURegs>;
320 /// Floating-point Aritmetic
321 defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
322 defm FDIV : FFR2P_M<0x03, "div", fdiv>;
323 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
324 defm FSUB : FFR2P_M<0x01, "sub", fsub>;
326 let Predicates = [HasMips32r2, HasStdEnc] in {
327 def MADD_S : FMADDSUB<0x4, 0, "madd", "s", fadd, FGR32>;
328 def MSUB_S : FMADDSUB<0x5, 0, "msub", "s", fsub, FGR32>;
331 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
332 def NMADD_S : FNMADDSUB<0x6, 0, "nmadd", "s", fadd, FGR32>;
333 def NMSUB_S : FNMADDSUB<0x7, 0, "nmsub", "s", fsub, FGR32>;
336 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
337 def MADD_D32 : FMADDSUB<0x4, 1, "madd", "d", fadd, AFGR64>;
338 def MSUB_D32 : FMADDSUB<0x5, 1, "msub", "d", fsub, AFGR64>;
341 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
342 def NMADD_D32 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, AFGR64>;
343 def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, AFGR64>;
346 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
347 def MADD_D64 : FMADDSUB<0x4, 1, "madd", "d", fadd, FGR64>;
348 def MSUB_D64 : FMADDSUB<0x5, 1, "msub", "d", fsub, FGR64>;
351 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
353 def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, FGR64>;
354 def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, FGR64>;
357 //===----------------------------------------------------------------------===//
358 // Floating Point Branch Codes
359 //===----------------------------------------------------------------------===//
360 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
361 // They must be kept in synch.
362 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
363 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
365 /// Floating Point Branch of False/True (Likely)
366 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
367 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
368 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
369 [(MipsFPBrcond op, bb:$dst)]> {
375 let DecoderMethod = "DecodeBC1" in {
376 def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
377 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
379 //===----------------------------------------------------------------------===//
380 // Floating Point Flag Conditions
381 //===----------------------------------------------------------------------===//
382 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
383 // They must be kept in synch.
384 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
385 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
386 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
387 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
388 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
389 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
390 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
391 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
392 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
393 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
394 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
395 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
396 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
397 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
398 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
399 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
401 class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
402 FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
403 !strconcat("c.$cc.", typestr, "\t$fs, $ft"),
404 [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
406 /// Floating Point Compare
407 let Defs=[FCR31] in {
408 def FCMP_S32 : FCMP<0x10, FGR32, "s">;
409 def FCMP_D32 : FCMP<0x11, AFGR64, "d">,
410 Requires<[NotFP64bit, HasStdEnc]>;
411 def FCMP_D64 : FCMP<0x11, FGR64, "d">,
412 Requires<[IsFP64bit, HasStdEnc]> {
413 let DecoderNamespace = "Mips64";
417 //===----------------------------------------------------------------------===//
418 // Floating Point Pseudo-Instructions
419 //===----------------------------------------------------------------------===//
420 def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src),
421 "# MOVCCRToCCR", []>;
423 // This pseudo instr gets expanded into 2 mtc1 instrs after register
426 PseudoSE<(outs AFGR64:$dst),
427 (ins CPURegs:$lo, CPURegs:$hi), "",
428 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
430 // This pseudo instr gets expanded into 2 mfc1 instrs after register
432 // if n is 0, lower part of src is extracted.
433 // if n is 1, higher part of src is extracted.
434 def ExtractElementF64 :
435 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "",
436 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
438 //===----------------------------------------------------------------------===//
439 // Floating Point Patterns
440 //===----------------------------------------------------------------------===//
441 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
442 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
444 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
445 def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
447 let Predicates = [NotFP64bit, HasStdEnc] in {
448 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
449 (CVT_D32_W (MTC1 CPURegs:$src))>;
450 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
451 (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
452 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
453 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
456 let Predicates = [IsFP64bit, HasStdEnc] in {
457 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
458 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
460 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
461 (CVT_D64_W (MTC1 CPURegs:$src))>;
462 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
463 (CVT_S_L (DMTC1 CPU64Regs:$src))>;
464 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
465 (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
467 def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
468 (MFC1 (TRUNC_W_D64 FGR64:$src))>;
469 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
470 def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
471 (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
473 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
474 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;