1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
42 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
43 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
44 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
45 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
46 [SDNPHasChain, SDNPOptInGlue]>;
47 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
48 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
49 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
50 SDT_MipsExtractElementF64>;
52 // Operand for printing out a condition code.
53 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
54 def condcode : Operand<i32>;
56 //===----------------------------------------------------------------------===//
57 // Feature predicates.
58 //===----------------------------------------------------------------------===//
60 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
61 AssemblerPredicate<"FeatureFP64Bit">;
62 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
63 AssemblerPredicate<"!FeatureFP64Bit">;
64 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
65 AssemblerPredicate<"FeatureSingleFloat">;
66 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
67 AssemblerPredicate<"!FeatureSingleFloat">;
69 // FP immediate patterns.
70 def fpimm0 : PatLeaf<(fpimm), [{
71 return N->isExactlyValue(+0.0);
74 def fpimm0neg : PatLeaf<(fpimm), [{
75 return N->isExactlyValue(-0.0);
78 //===----------------------------------------------------------------------===//
79 // Instruction Class Templates
81 // A set of multiclasses is used to address the register usage.
83 // S32 - single precision in 16 32bit even fp registers
84 // single precision in 32 32bit fp registers in SingleOnly mode
85 // S64 - single precision in 32 64bit fp registers (In64BitMode)
86 // D32 - double precision in 16 32bit even fp registers
87 // D64 - double precision in 32 64bit fp registers (In64BitMode)
89 // Only S32 and D32 are supported right now.
90 //===----------------------------------------------------------------------===//
92 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
93 SDPatternOperator OpNode= null_frag> :
94 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
95 !strconcat(opstr, "\t$fd, $fs, $ft"),
96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
97 let isCommutable = IsComm;
100 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
101 SDPatternOperator OpNode = null_frag> {
102 def _D32 : ADDS_FT<opstr, AFGR64RegsOpnd, Itin, IsComm, OpNode>,
103 Requires<[NotFP64bit, HasStdEnc]>;
104 def _D64 : ADDS_FT<opstr, FGR64RegsOpnd, Itin, IsComm, OpNode>,
105 Requires<[IsFP64bit, HasStdEnc]> {
106 string DecoderNamespace = "Mips64";
110 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
111 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
112 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
113 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
116 multiclass ABSS_M<string opstr, InstrItinClass Itin,
117 SDPatternOperator OpNode= null_frag> {
118 def _D32 : ABSS_FT<opstr, AFGR64RegsOpnd, AFGR64RegsOpnd, Itin, OpNode>,
119 Requires<[NotFP64bit, HasStdEnc]>;
120 def _D64 : ABSS_FT<opstr, FGR64RegsOpnd, FGR64RegsOpnd, Itin, OpNode>,
121 Requires<[IsFP64bit, HasStdEnc]> {
122 string DecoderNamespace = "Mips64";
126 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
127 def _D32 : ABSS_FT<opstr, FGR32RegsOpnd, AFGR64RegsOpnd, Itin>,
128 Requires<[NotFP64bit, HasStdEnc]>;
129 def _D64 : ABSS_FT<opstr, FGR32RegsOpnd, FGR64RegsOpnd, Itin>,
130 Requires<[IsFP64bit, HasStdEnc]> {
131 let DecoderNamespace = "Mips64";
135 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
136 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
137 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
138 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
140 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
141 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
142 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
143 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
145 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
146 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
147 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
148 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
149 let DecoderMethod = "DecodeFMem";
153 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
154 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
155 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
156 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
157 let DecoderMethod = "DecodeFMem";
161 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
162 SDPatternOperator OpNode = null_frag> :
163 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
164 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
165 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
167 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
168 SDPatternOperator OpNode = null_frag> :
169 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
170 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
171 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
174 class LWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
175 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
176 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
177 !strconcat(opstr, "\t$fd, ${index}(${base})"),
178 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
179 let AddedComplexity = 20;
182 class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC,
183 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
184 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
185 !strconcat(opstr, "\t$fs, ${index}(${base})"),
186 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
187 let AddedComplexity = 20;
190 class BC1F_FT<string opstr, InstrItinClass Itin,
191 SDPatternOperator Op = null_frag> :
192 InstSE<(outs), (ins FCC:$fcc, brtarget:$offset),
193 !strconcat(opstr, "\t$fcc, $offset"),
194 [(MipsFPBrcond Op, FCC:$fcc, bb:$offset)], Itin, FrmFI> {
196 let isTerminator = 1;
197 let hasDelaySlot = 1;
201 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
202 SDPatternOperator OpNode = null_frag> :
203 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
204 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
205 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
207 let isCodeGenOnly = 1;
210 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> :
211 InstSE<(outs), (ins RC:$fs, RC:$ft),
212 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp,
215 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> {
216 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>;
217 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>;
218 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>;
219 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>;
220 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>;
221 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>;
222 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>;
223 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>;
224 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>;
225 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>;
226 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>;
227 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>;
228 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>;
229 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>;
230 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>;
231 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>;
234 defm S : C_COND_M<"s", FGR32RegsOpnd, 16>;
235 defm D32 : C_COND_M<"d", AFGR64RegsOpnd, 17>,
236 Requires<[NotFP64bit, HasStdEnc]>;
237 let DecoderNamespace = "Mips64" in
238 defm D64 : C_COND_M<"d", FGR64RegsOpnd, 17>, Requires<[IsFP64bit, HasStdEnc]>;
240 //===----------------------------------------------------------------------===//
241 // Floating Point Instructions
242 //===----------------------------------------------------------------------===//
243 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
245 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
247 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
249 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
251 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
254 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
255 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
256 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
257 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
258 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
260 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
261 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
263 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
265 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
267 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
269 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
271 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
273 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
275 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
279 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt>,
281 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
283 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
286 let Predicates = [NotFP64bit, HasStdEnc] in {
287 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, AFGR64RegsOpnd, IIFcvt>,
289 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
291 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
295 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
296 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
298 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32RegsOpnd, FGR64RegsOpnd, IIFcvt>,
300 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
302 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64RegsOpnd, FGR32RegsOpnd, IIFcvt>,
304 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64RegsOpnd, FGR64RegsOpnd, IIFcvt>,
308 let isPseudo = 1, isCodeGenOnly = 1 in {
309 def PseudoCVT_S_W : ABSS_FT<"", FGR32RegsOpnd, CPURegsOpnd, IIFcvt>;
310 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64RegsOpnd, CPURegsOpnd, IIFcvt>;
311 def PseudoCVT_S_L : ABSS_FT<"", FGR64RegsOpnd, CPU64RegsOpnd, IIFcvt>;
312 def PseudoCVT_D64_W : ABSS_FT<"", FGR64RegsOpnd, CPURegsOpnd, IIFcvt>;
313 def PseudoCVT_D64_L : ABSS_FT<"", FGR64RegsOpnd, CPU64RegsOpnd, IIFcvt>;
316 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
317 def FABS_S : ABSS_FT<"abs.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fabs>,
319 def FNEG_S : ABSS_FT<"neg.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFcvt, fneg>,
321 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
322 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
325 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFsqrtSingle,
326 fsqrt>, ABSS_FM<0x4, 16>;
327 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
329 // The odd-numbered registers are only referenced when doing loads,
330 // stores, and moves between floating-point and integer registers.
331 // When defining instructions, we reference all 32-bit registers,
332 // regardless of register aliasing.
334 /// Move Control Registers From/To CPU Registers
335 def CFC1 : MFC1_FT<"cfc1", CPURegsOpnd, CCROpnd, IIFmove>, MFC1_FM<2>;
336 def CTC1 : MTC1_FT<"ctc1", CCROpnd, CPURegsOpnd, IIFmove>, MFC1_FM<6>;
337 def MFC1 : MFC1_FT<"mfc1", CPURegsOpnd, FGR32RegsOpnd, IIFmoveC1, bitconvert>,
339 def MTC1 : MTC1_FT<"mtc1", FGR32RegsOpnd, CPURegsOpnd, IIFmoveC1, bitconvert>,
341 def DMFC1 : MFC1_FT<"dmfc1", CPU64RegsOpnd, FGR64RegsOpnd, IIFmoveC1,
342 bitconvert>, MFC1_FM<1>;
343 def DMTC1 : MTC1_FT<"dmtc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFmoveC1,
344 bitconvert>, MFC1_FM<5>;
346 def FMOV_S : ABSS_FT<"mov.s", FGR32RegsOpnd, FGR32RegsOpnd, IIFmove>,
348 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64RegsOpnd, AFGR64RegsOpnd, IIFmove>,
349 ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>;
350 def FMOV_D64 : ABSS_FT<"mov.d", FGR64RegsOpnd, FGR64RegsOpnd, IIFmove>,
351 ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> {
352 let DecoderNamespace = "Mips64";
355 /// Floating Point Memory Instructions
356 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
357 def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem64, load>,
359 def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem64, store>,
361 def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem64, load>,
363 let isCodeGenOnly =1;
365 def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem64, store>,
367 let isCodeGenOnly =1;
371 let Predicates = [NotN64, HasStdEnc] in {
372 def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem, load>, LW_FM<0x31>;
373 def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem, store>, LW_FM<0x39>;
376 let Predicates = [NotN64, HasMips64, HasStdEnc],
377 DecoderNamespace = "Mips64" in {
378 def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem, load>, LW_FM<0x35>;
379 def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem, store>, LW_FM<0x3d>;
382 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
383 let isPseudo = 1, isCodeGenOnly = 1 in {
384 def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IIFLoad, mem, load>;
385 def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIFStore, mem, store>;
387 def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IIFLoad, mem>, LW_FM<0x35>;
388 def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIFStore, mem>, LW_FM<0x3d>;
391 // Indexed loads and stores.
392 let Predicates = [HasFPIdx, HasStdEnc] in {
393 def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IIFLoad, load>,
395 def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIFStore, store>,
399 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
400 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>,
402 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore, store>,
406 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
407 def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>,
409 def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore, store>,
414 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
415 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFLoad, load>,
417 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFLoad,
419 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFStore,
421 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFStore,
425 // Load/store doubleword indexed unaligned.
426 let Predicates = [NotMips64, HasStdEnc] in {
427 def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad>,
429 def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore>,
433 let Predicates = [HasMips64, HasStdEnc],
434 DecoderNamespace="Mips64" in {
435 def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad>,
437 def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore>,
441 /// Floating-point Aritmetic
442 def FADD_S : ADDS_FT<"add.s", FGR32RegsOpnd, IIFadd, 1, fadd>,
444 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
445 def FDIV_S : ADDS_FT<"div.s", FGR32RegsOpnd, IIFdivSingle, 0, fdiv>,
447 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
448 def FMUL_S : ADDS_FT<"mul.s", FGR32RegsOpnd, IIFmulSingle, 1, fmul>,
450 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
451 def FSUB_S : ADDS_FT<"sub.s", FGR32RegsOpnd, IIFadd, 0, fsub>,
453 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
455 let Predicates = [HasMips32r2, HasStdEnc] in {
456 def MADD_S : MADDS_FT<"madd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
458 def MSUB_S : MADDS_FT<"msub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
462 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
463 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32RegsOpnd, IIFmulSingle, fadd>,
465 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32RegsOpnd, IIFmulSingle, fsub>,
469 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
470 def MADD_D32 : MADDS_FT<"madd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
472 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
476 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
477 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64RegsOpnd, IIFmulDouble, fadd>,
479 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64RegsOpnd, IIFmulDouble, fsub>,
483 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
484 def MADD_D64 : MADDS_FT<"madd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
486 def MSUB_D64 : MADDS_FT<"msub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
490 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
492 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64RegsOpnd, IIFmulDouble, fadd>,
494 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64RegsOpnd, IIFmulDouble, fsub>,
498 //===----------------------------------------------------------------------===//
499 // Floating Point Branch Codes
500 //===----------------------------------------------------------------------===//
501 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
502 // They must be kept in synch.
503 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
504 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
506 def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
507 def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
509 //===----------------------------------------------------------------------===//
510 // Floating Point Flag Conditions
511 //===----------------------------------------------------------------------===//
512 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
513 // They must be kept in synch.
514 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
515 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
516 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
517 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
518 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
519 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
520 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
521 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
522 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
523 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
524 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
525 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
526 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
527 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
528 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
529 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
531 /// Floating Point Compare
532 def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
533 def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
534 Requires<[NotFP64bit, HasStdEnc]>;
535 let DecoderNamespace = "Mips64" in
536 def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
537 Requires<[IsFP64bit, HasStdEnc]>;
539 //===----------------------------------------------------------------------===//
540 // Floating Point Pseudo-Instructions
541 //===----------------------------------------------------------------------===//
543 // This pseudo instr gets expanded into 2 mtc1 instrs after register
546 PseudoSE<(outs AFGR64RegsOpnd:$dst),
547 (ins CPURegsOpnd:$lo, CPURegsOpnd:$hi),
548 [(set AFGR64RegsOpnd:$dst,
549 (MipsBuildPairF64 CPURegsOpnd:$lo, CPURegsOpnd:$hi))]>;
551 // This pseudo instr gets expanded into 2 mfc1 instrs after register
553 // if n is 0, lower part of src is extracted.
554 // if n is 1, higher part of src is extracted.
555 def ExtractElementF64 :
556 PseudoSE<(outs CPURegsOpnd:$dst), (ins AFGR64RegsOpnd:$src, i32imm:$n),
557 [(set CPURegsOpnd:$dst,
558 (MipsExtractElementF64 AFGR64RegsOpnd:$src, imm:$n))]>;
560 //===----------------------------------------------------------------------===//
562 //===----------------------------------------------------------------------===//
563 def : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>;
564 def : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>;
566 //===----------------------------------------------------------------------===//
567 // Floating Point Patterns
568 //===----------------------------------------------------------------------===//
569 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
570 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
572 def : MipsPat<(f32 (sint_to_fp CPURegsOpnd:$src)),
573 (PseudoCVT_S_W CPURegsOpnd:$src)>;
574 def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
575 (TRUNC_W_S FGR32RegsOpnd:$src)>;
577 let Predicates = [NotFP64bit, HasStdEnc] in {
578 def : MipsPat<(f64 (sint_to_fp CPURegsOpnd:$src)),
579 (PseudoCVT_D32_W CPURegsOpnd:$src)>;
580 def : MipsPat<(MipsTruncIntFP AFGR64RegsOpnd:$src),
581 (TRUNC_W_D32 AFGR64RegsOpnd:$src)>;
582 def : MipsPat<(f32 (fround AFGR64RegsOpnd:$src)),
583 (CVT_S_D32 AFGR64RegsOpnd:$src)>;
584 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
585 (CVT_D32_S FGR32RegsOpnd:$src)>;
588 let Predicates = [IsFP64bit, HasStdEnc] in {
589 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
590 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
592 def : MipsPat<(f64 (sint_to_fp CPURegsOpnd:$src)),
593 (PseudoCVT_D64_W CPURegsOpnd:$src)>;
594 def : MipsPat<(f32 (sint_to_fp CPU64RegsOpnd:$src)),
595 (EXTRACT_SUBREG (PseudoCVT_S_L CPU64RegsOpnd:$src), sub_32)>;
596 def : MipsPat<(f64 (sint_to_fp CPU64RegsOpnd:$src)),
597 (PseudoCVT_D64_L CPU64RegsOpnd:$src)>;
599 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
600 (TRUNC_W_D64 FGR64RegsOpnd:$src)>;
601 def : MipsPat<(MipsTruncIntFP FGR32RegsOpnd:$src),
602 (TRUNC_L_S FGR32RegsOpnd:$src)>;
603 def : MipsPat<(MipsTruncIntFP FGR64RegsOpnd:$src),
604 (TRUNC_L_D64 FGR64RegsOpnd:$src)>;
606 def : MipsPat<(f32 (fround FGR64RegsOpnd:$src)),
607 (CVT_S_D64 FGR64RegsOpnd:$src)>;
608 def : MipsPat<(f64 (fextend FGR32RegsOpnd:$src)),
609 (CVT_D64_S FGR32RegsOpnd:$src)>;
612 // Patterns for loads/stores with a reg+imm operand.
613 let AddedComplexity = 40 in {
614 let Predicates = [IsN64, HasStdEnc] in {
615 def : LoadRegImmPat<LWC1_P8, f32, load>;
616 def : StoreRegImmPat<SWC1_P8, f32>;
617 def : LoadRegImmPat<LDC164_P8, f64, load>;
618 def : StoreRegImmPat<SDC164_P8, f64>;
621 let Predicates = [NotN64, HasStdEnc] in {
622 def : LoadRegImmPat<LWC1, f32, load>;
623 def : StoreRegImmPat<SWC1, f32>;
626 let Predicates = [NotN64, HasMips64, HasStdEnc] in {
627 def : LoadRegImmPat<LDC164, f64, load>;
628 def : StoreRegImmPat<SDC164, f64>;
631 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
632 def : LoadRegImmPat<PseudoLDC1, f64, load>;
633 def : StoreRegImmPat<PseudoSDC1, f64>;