1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
58 AssemblerPredicate<"FeatureFP64Bit">;
59 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
60 AssemblerPredicate<"!FeatureFP64Bit">;
61 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
62 AssemblerPredicate<"FeatureSingleFloat">;
63 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"!FeatureSingleFloat">;
66 // FP immediate patterns.
67 def fpimm0 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+0.0);
71 def fpimm0neg : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-0.0);
75 //===----------------------------------------------------------------------===//
76 // Instruction Class Templates
78 // A set of multiclasses is used to address the register usage.
80 // S32 - single precision in 16 32bit even fp registers
81 // single precision in 32 32bit fp registers in SingleOnly mode
82 // S64 - single precision in 32 64bit fp registers (In64BitMode)
83 // D32 - double precision in 16 32bit even fp registers
84 // D64 - double precision in 32 64bit fp registers (In64BitMode)
86 // Only S32 and D32 are supported right now.
87 //===----------------------------------------------------------------------===//
89 // FP unary instructions without patterns.
90 class FFR1<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
91 RegisterClass SrcRC> :
92 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
93 !strconcat(opstr, "\t$fd, $fs"), []> {
97 // FP unary instructions with patterns.
98 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
99 RegisterClass SrcRC, SDNode OpNode> :
100 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
101 !strconcat(opstr, "\t$fd, $fs"),
102 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
106 class FFR2P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass RC,
108 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
109 !strconcat(opstr, "\t$fd, $fs, $ft"),
110 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
113 let DecoderMethod = "DecodeFMem" in {
114 class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
115 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
116 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))],
120 class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
121 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
122 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
126 class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
127 RegisterClass PRC, SDPatternOperator FOp = null_frag>:
128 FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
129 !strconcat(opstr, "\t$fd, ${index}(${base})"),
130 [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
135 class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
136 RegisterClass PRC, SDPatternOperator FOp= null_frag>:
137 FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
138 !strconcat(opstr, "\t$fs, ${index}(${base})"),
139 [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
143 // Instructions that convert an FP value to 32-bit fixed point.
144 multiclass FFR1_W_M<bits<6> funct, string opstr> {
145 def _D32 : FFR1<funct, 17, opstr, FGR32, AFGR64>,
146 Requires<[NotFP64bit, HasStdEnc]>;
147 def _D64 : FFR1<funct, 17, opstr, FGR32, FGR64>,
148 Requires<[IsFP64bit, HasStdEnc]> {
149 let DecoderNamespace = "Mips64";
153 // FP-to-FP conversion instructions.
154 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
155 def _D32 : FFR1P<funct, 17, opstr, AFGR64, AFGR64, OpNode>,
156 Requires<[NotFP64bit, HasStdEnc]>;
157 def _D64 : FFR1P<funct, 17, opstr, FGR64, FGR64, OpNode>,
158 Requires<[IsFP64bit, HasStdEnc]> {
159 let DecoderNamespace = "Mips64";
163 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode> {
164 def _D32 : FFR2P<funct, 17, opstr, AFGR64, OpNode>,
165 Requires<[NotFP64bit, HasStdEnc]>;
166 def _D64 : FFR2P<funct, 17, opstr, FGR64, OpNode>,
167 Requires<[IsFP64bit, HasStdEnc]> {
168 let DecoderNamespace = "Mips64";
172 // FP madd/msub/nmadd/nmsub instruction classes.
173 class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
174 SDNode OpNode, RegisterClass RC> :
175 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
176 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
177 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>;
179 class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
180 SDNode OpNode, RegisterClass RC> :
181 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
182 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
183 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>;
185 class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
186 SDPatternOperator OpNode= null_frag> :
187 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
188 !strconcat(opstr, "\t$fd, $fs, $ft"),
189 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
190 let isCommutable = IsComm;
193 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
194 SDPatternOperator OpNode = null_frag> {
195 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
196 Requires<[NotFP64bit, HasStdEnc]>;
197 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
198 Requires<[IsFP64bit, HasStdEnc]> {
199 string DecoderNamespace = "Mips64";
203 class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
204 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
205 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
206 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>;
208 multiclass ABSS_M<string opstr, InstrItinClass Itin,
209 SDPatternOperator OpNode= null_frag> {
210 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
211 Requires<[NotFP64bit, HasStdEnc]>;
212 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
213 Requires<[IsFP64bit, HasStdEnc]> {
214 string DecoderNamespace = "Mips64";
218 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
219 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
220 Requires<[NotFP64bit, HasStdEnc]>;
221 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
222 Requires<[IsFP64bit, HasStdEnc]> {
223 let DecoderNamespace = "Mips64";
227 class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
228 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
229 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
230 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
232 class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
233 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
234 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
235 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
237 class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
238 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
239 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
240 [(set RC:$rt, (OpNode addr:$addr))], Itin, FrmFI> {
241 let DecoderMethod = "DecodeFMem";
244 class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
245 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
246 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
247 [(OpNode RC:$rt, addr:$addr)], Itin, FrmFI> {
248 let DecoderMethod = "DecodeFMem";
251 class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
252 SDPatternOperator OpNode = null_frag> :
253 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
254 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
255 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
257 class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
258 SDPatternOperator OpNode = null_frag> :
259 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
260 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
261 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
264 class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
265 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
266 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
267 !strconcat(opstr, "\t$fd, ${index}(${base})"),
268 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI>;
270 class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
271 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
272 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
273 !strconcat(opstr, "\t$fs, ${index}(${base})"),
274 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>;
276 class BC1F_FT<string opstr, InstrItinClass Itin,
277 SDPatternOperator Op = null_frag> :
278 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
279 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
281 let isTerminator = 1;
282 let hasDelaySlot = 1;
287 //===----------------------------------------------------------------------===//
288 // Floating Point Instructions
289 //===----------------------------------------------------------------------===//
290 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
291 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
292 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
293 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
294 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>,
297 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
298 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
299 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
300 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
301 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>,
304 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
305 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
306 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
308 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
309 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
311 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
312 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
313 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
314 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
318 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
319 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>,
321 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>,
324 let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in {
325 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
326 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
327 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
330 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64",
331 neverHasSideEffects = 1 in {
332 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
333 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
334 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
335 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
336 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
339 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
340 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
341 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
342 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
343 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
346 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
348 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
350 // The odd-numbered registers are only referenced when doing loads,
351 // stores, and moves between floating-point and integer registers.
352 // When defining instructions, we reference all 32-bit registers,
353 // regardless of register aliasing.
355 class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
356 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
362 /// Move Control Registers From/To CPU Registers
363 def CFC1 : MFC1_FT<"cfc1", CPURegs, CCR, IIFmove>, MFC1_FM<2>;
364 def CTC1 : MTC1_FT<"ctc1", CCR, CPURegs, IIFmove>, MFC1_FM<6>;
365 def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
366 def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
367 def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
368 def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
370 def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
371 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
372 Requires<[NotFP64bit, HasStdEnc]>;
373 def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
374 Requires<[IsFP64bit, HasStdEnc]> {
375 let DecoderNamespace = "Mips64";
378 /// Floating Point Memory Instructions
379 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
380 def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
381 def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
382 def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
383 let isCodeGenOnly =1;
385 def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
386 let isCodeGenOnly =1;
390 let Predicates = [NotN64, HasStdEnc] in {
391 def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
392 def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
395 let Predicates = [NotN64, HasMips64, HasStdEnc],
396 DecoderNamespace = "Mips64" in {
397 def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
398 def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
401 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
402 def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem, load>, LW_FM<0x35>;
403 def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem, store>, LW_FM<0x3d>;
406 // Indexed loads and stores.
407 let Predicates = [HasFPIdx, HasStdEnc] in {
408 def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
409 def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
412 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
413 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
414 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
417 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
418 def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
419 def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
423 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
424 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
425 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
427 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
429 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
433 // Load/store doubleword indexed unaligned.
434 let Predicates = [NotMips64, HasStdEnc] in {
435 def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
436 def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
439 let Predicates = [HasMips64, HasStdEnc],
440 DecoderNamespace="Mips64" in {
441 def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
442 def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
445 /// Floating-point Aritmetic
446 def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
447 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
448 def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
449 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
450 def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
451 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
452 def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
453 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
455 let Predicates = [HasMips32r2, HasStdEnc] in {
456 def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
457 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
460 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
461 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
462 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
465 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
466 def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
467 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
470 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
471 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
473 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
477 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
478 def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
479 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
482 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
484 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
486 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
490 //===----------------------------------------------------------------------===//
491 // Floating Point Branch Codes
492 //===----------------------------------------------------------------------===//
493 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
494 // They must be kept in synch.
495 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
496 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
498 /// Floating Point Branch of False/True (Likely)
499 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
500 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
501 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
502 [(MipsFPBrcond op, bb:$dst)]> {
508 let DecoderMethod = "DecodeBC1" in {
509 def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
510 def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
512 //===----------------------------------------------------------------------===//
513 // Floating Point Flag Conditions
514 //===----------------------------------------------------------------------===//
515 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
516 // They must be kept in synch.
517 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
518 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
519 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
520 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
521 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
522 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
523 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
524 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
525 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
526 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
527 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
528 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
529 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
530 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
531 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
532 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
534 class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
535 FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
536 !strconcat("c.$cc.", typestr, "\t$fs, $ft"),
537 [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
539 /// Floating Point Compare
540 let Defs=[FCR31] in {
541 def FCMP_S32 : FCMP<0x10, FGR32, "s">;
542 def FCMP_D32 : FCMP<0x11, AFGR64, "d">,
543 Requires<[NotFP64bit, HasStdEnc]>;
544 def FCMP_D64 : FCMP<0x11, FGR64, "d">,
545 Requires<[IsFP64bit, HasStdEnc]> {
546 let DecoderNamespace = "Mips64";
550 //===----------------------------------------------------------------------===//
551 // Floating Point Pseudo-Instructions
552 //===----------------------------------------------------------------------===//
553 def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src),
554 "# MOVCCRToCCR", []>;
556 // This pseudo instr gets expanded into 2 mtc1 instrs after register
559 PseudoSE<(outs AFGR64:$dst),
560 (ins CPURegs:$lo, CPURegs:$hi), "",
561 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
563 // This pseudo instr gets expanded into 2 mfc1 instrs after register
565 // if n is 0, lower part of src is extracted.
566 // if n is 1, higher part of src is extracted.
567 def ExtractElementF64 :
568 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "",
569 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
571 //===----------------------------------------------------------------------===//
572 // Floating Point Patterns
573 //===----------------------------------------------------------------------===//
574 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
575 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
577 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
578 def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
580 let Predicates = [NotFP64bit, HasStdEnc] in {
581 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
582 (CVT_D32_W (MTC1 CPURegs:$src))>;
583 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
584 (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
585 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
586 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
589 let Predicates = [IsFP64bit, HasStdEnc] in {
590 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
591 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
593 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
594 (CVT_D64_W (MTC1 CPURegs:$src))>;
595 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
596 (CVT_S_L (DMTC1 CPU64Regs:$src))>;
597 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
598 (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
600 def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
601 (MFC1 (TRUNC_W_D64 FGR64:$src))>;
602 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
603 def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
604 (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
606 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
607 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;