1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
58 AssemblerPredicate<"FeatureFP64Bit">;
59 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
60 AssemblerPredicate<"!FeatureFP64Bit">;
61 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
62 AssemblerPredicate<"FeatureSingleFloat">;
63 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"!FeatureSingleFloat">;
66 // FP immediate patterns.
67 def fpimm0 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+0.0);
71 def fpimm0neg : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-0.0);
75 //===----------------------------------------------------------------------===//
76 // Instruction Class Templates
78 // A set of multiclasses is used to address the register usage.
80 // S32 - single precision in 16 32bit even fp registers
81 // single precision in 32 32bit fp registers in SingleOnly mode
82 // S64 - single precision in 32 64bit fp registers (In64BitMode)
83 // D32 - double precision in 16 32bit even fp registers
84 // D64 - double precision in 32 64bit fp registers (In64BitMode)
86 // Only S32 and D32 are supported right now.
87 //===----------------------------------------------------------------------===//
89 class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
90 SDPatternOperator OpNode= null_frag> :
91 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
92 !strconcat(opstr, "\t$fd, $fs, $ft"),
93 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
94 let isCommutable = IsComm;
97 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
98 SDPatternOperator OpNode = null_frag> {
99 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
100 Requires<[NotFP64bit, HasStdEnc]>;
101 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
102 Requires<[IsFP64bit, HasStdEnc]> {
103 string DecoderNamespace = "Mips64";
107 class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
108 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
109 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
110 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
113 multiclass ABSS_M<string opstr, InstrItinClass Itin,
114 SDPatternOperator OpNode= null_frag> {
115 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
116 Requires<[NotFP64bit, HasStdEnc]>;
117 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
118 Requires<[IsFP64bit, HasStdEnc]> {
119 string DecoderNamespace = "Mips64";
123 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
124 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
125 Requires<[NotFP64bit, HasStdEnc]>;
126 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
127 Requires<[IsFP64bit, HasStdEnc]> {
128 let DecoderNamespace = "Mips64";
132 class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
133 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
134 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
135 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
137 class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
138 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
139 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
140 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
142 class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC,
143 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
144 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
145 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
147 class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
148 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
149 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
150 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
152 class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
153 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
154 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
155 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
156 let DecoderMethod = "DecodeFMem";
160 class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
161 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
162 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
163 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
164 let DecoderMethod = "DecodeFMem";
168 class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
169 SDPatternOperator OpNode = null_frag> :
170 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
171 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
172 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
174 class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
175 SDPatternOperator OpNode = null_frag> :
176 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
177 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
178 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
181 class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
182 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
183 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
184 !strconcat(opstr, "\t$fd, ${index}(${base})"),
185 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
186 let AddedComplexity = 20;
189 class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
190 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
191 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
192 !strconcat(opstr, "\t$fs, ${index}(${base})"),
193 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
194 let AddedComplexity = 20;
197 class BC1F_FT<string opstr, InstrItinClass Itin,
198 SDPatternOperator Op = null_frag> :
199 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
200 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
202 let isTerminator = 1;
203 let hasDelaySlot = 1;
208 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
209 SDPatternOperator OpNode = null_frag> :
210 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
211 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
212 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
216 //===----------------------------------------------------------------------===//
217 // Floating Point Instructions
218 //===----------------------------------------------------------------------===//
219 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
220 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
221 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
222 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
223 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>;
225 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
226 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
227 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
228 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
229 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
231 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
232 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
233 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
235 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
236 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
238 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
239 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
240 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
241 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
245 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
246 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>;
247 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>;
249 let Predicates = [NotFP64bit, HasStdEnc] in {
250 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
251 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
252 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
255 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
256 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
257 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
258 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
259 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
260 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
263 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
264 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
265 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
266 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
267 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
270 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
272 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
274 // The odd-numbered registers are only referenced when doing loads,
275 // stores, and moves between floating-point and integer registers.
276 // When defining instructions, we reference all 32-bit registers,
277 // regardless of register aliasing.
279 /// Move Control Registers From/To CPU Registers
280 def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
281 def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
282 def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
283 def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
284 def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
285 def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
287 def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
288 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
289 Requires<[NotFP64bit, HasStdEnc]>;
290 def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
291 Requires<[IsFP64bit, HasStdEnc]> {
292 let DecoderNamespace = "Mips64";
295 /// Floating Point Memory Instructions
296 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
297 def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
298 def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
299 def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
300 let isCodeGenOnly =1;
302 def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
303 let isCodeGenOnly =1;
307 let Predicates = [NotN64, HasStdEnc] in {
308 def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
309 def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
312 let Predicates = [NotN64, HasMips64, HasStdEnc],
313 DecoderNamespace = "Mips64" in {
314 def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
315 def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
318 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
319 let isPseudo = 1, isCodeGenOnly = 1 in {
320 def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>;
321 def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>;
323 def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>;
324 def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>;
327 // Indexed loads and stores.
328 let Predicates = [HasFPIdx, HasStdEnc] in {
329 def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
330 def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
333 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
334 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
335 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
338 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
339 def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
340 def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
344 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
345 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
346 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
348 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
350 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
354 // Load/store doubleword indexed unaligned.
355 let Predicates = [NotMips64, HasStdEnc] in {
356 def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
357 def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
360 let Predicates = [HasMips64, HasStdEnc],
361 DecoderNamespace="Mips64" in {
362 def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
363 def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
366 /// Floating-point Aritmetic
367 def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
368 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
369 def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
370 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
371 def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
372 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
373 def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
374 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
376 let Predicates = [HasMips32r2, HasStdEnc] in {
377 def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
378 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
381 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
382 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
383 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
386 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
387 def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
388 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
391 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
392 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
394 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
398 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
399 def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
400 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
403 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
405 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
407 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
411 //===----------------------------------------------------------------------===//
412 // Floating Point Branch Codes
413 //===----------------------------------------------------------------------===//
414 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
415 // They must be kept in synch.
416 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
417 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
419 let DecoderMethod = "DecodeBC1" in {
420 def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
421 def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
423 //===----------------------------------------------------------------------===//
424 // Floating Point Flag Conditions
425 //===----------------------------------------------------------------------===//
426 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
427 // They must be kept in synch.
428 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
429 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
430 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
431 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
432 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
433 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
434 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
435 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
436 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
437 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
438 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
439 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
440 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
441 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
442 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
443 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
445 /// Floating Point Compare
446 def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
447 def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
448 Requires<[NotFP64bit, HasStdEnc]>;
449 let DecoderNamespace = "Mips64" in
450 def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
451 Requires<[IsFP64bit, HasStdEnc]>;
453 //===----------------------------------------------------------------------===//
454 // Floating Point Pseudo-Instructions
455 //===----------------------------------------------------------------------===//
456 def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>;
458 // This pseudo instr gets expanded into 2 mtc1 instrs after register
461 PseudoSE<(outs AFGR64:$dst),
462 (ins CPURegs:$lo, CPURegs:$hi),
463 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
465 // This pseudo instr gets expanded into 2 mfc1 instrs after register
467 // if n is 0, lower part of src is extracted.
468 // if n is 1, higher part of src is extracted.
469 def ExtractElementF64 :
470 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n),
471 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
473 //===----------------------------------------------------------------------===//
474 // Floating Point Patterns
475 //===----------------------------------------------------------------------===//
476 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
477 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
479 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
480 def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
482 let Predicates = [NotFP64bit, HasStdEnc] in {
483 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
484 (CVT_D32_W (MTC1 CPURegs:$src))>;
485 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
486 (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
487 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
488 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
491 let Predicates = [IsFP64bit, HasStdEnc] in {
492 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
493 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
495 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
496 (CVT_D64_W (MTC1 CPURegs:$src))>;
497 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
498 (CVT_S_L (DMTC1 CPU64Regs:$src))>;
499 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
500 (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
502 def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
503 (MFC1 (TRUNC_W_D64 FGR64:$src))>;
504 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
505 def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
506 (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
508 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
509 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
512 // Patterns for loads/stores with a reg+imm operand.
513 let AddedComplexity = 40 in {
514 let Predicates = [IsN64, HasStdEnc] in {
515 def : LoadRegImmPat<LWC1_P8, f32, load>;
516 def : StoreRegImmPat<SWC1_P8, f32>;
517 def : LoadRegImmPat<LDC164_P8, f64, load>;
518 def : StoreRegImmPat<SDC164_P8, f64>;
521 let Predicates = [NotN64, HasStdEnc] in {
522 def : LoadRegImmPat<LWC1, f32, load>;
523 def : StoreRegImmPat<SWC1, f32>;
526 let Predicates = [NotN64, HasMips64, HasStdEnc] in {
527 def : LoadRegImmPat<LDC164, f64, load>;
528 def : StoreRegImmPat<SDC164, f64>;
531 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
532 def : LoadRegImmPat<PseudoLDC1, f64, load>;
533 def : StoreRegImmPat<PseudoSDC1, f64>;