1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
58 AssemblerPredicate<"FeatureFP64Bit">;
59 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
60 AssemblerPredicate<"!FeatureFP64Bit">;
61 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
62 AssemblerPredicate<"FeatureSingleFloat">;
63 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"!FeatureSingleFloat">;
66 // FP immediate patterns.
67 def fpimm0 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+0.0);
71 def fpimm0neg : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-0.0);
75 //===----------------------------------------------------------------------===//
76 // Instruction Class Templates
78 // A set of multiclasses is used to address the register usage.
80 // S32 - single precision in 16 32bit even fp registers
81 // single precision in 32 32bit fp registers in SingleOnly mode
82 // S64 - single precision in 32 64bit fp registers (In64BitMode)
83 // D32 - double precision in 16 32bit even fp registers
84 // D64 - double precision in 32 64bit fp registers (In64BitMode)
86 // Only S32 and D32 are supported right now.
87 //===----------------------------------------------------------------------===//
89 // FP unary instructions without patterns.
90 class FFR1<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
91 RegisterClass SrcRC> :
92 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
93 !strconcat(opstr, "\t$fd, $fs"), []> {
97 // FP unary instructions with patterns.
98 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass DstRC,
99 RegisterClass SrcRC, SDNode OpNode> :
100 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
101 !strconcat(opstr, "\t$fd, $fs"),
102 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
106 class FFR2P<bits<6> funct, bits<5> fmt, string opstr, RegisterClass RC,
108 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
109 !strconcat(opstr, "\t$fd, $fs, $ft"),
110 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
113 let DecoderMethod = "DecodeFMem" in {
114 class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
115 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
116 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))],
120 class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
121 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
122 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
126 class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
127 RegisterClass PRC, SDPatternOperator FOp = null_frag>:
128 FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
129 !strconcat(opstr, "\t$fd, ${index}(${base})"),
130 [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
135 class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
136 RegisterClass PRC, SDPatternOperator FOp= null_frag>:
137 FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
138 !strconcat(opstr, "\t$fs, ${index}(${base})"),
139 [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
143 // Instructions that convert an FP value to 32-bit fixed point.
144 multiclass FFR1_W_M<bits<6> funct, string opstr> {
145 def _D32 : FFR1<funct, 17, opstr, FGR32, AFGR64>,
146 Requires<[NotFP64bit, HasStdEnc]>;
147 def _D64 : FFR1<funct, 17, opstr, FGR32, FGR64>,
148 Requires<[IsFP64bit, HasStdEnc]> {
149 let DecoderNamespace = "Mips64";
153 // FP-to-FP conversion instructions.
154 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
155 def _D32 : FFR1P<funct, 17, opstr, AFGR64, AFGR64, OpNode>,
156 Requires<[NotFP64bit, HasStdEnc]>;
157 def _D64 : FFR1P<funct, 17, opstr, FGR64, FGR64, OpNode>,
158 Requires<[IsFP64bit, HasStdEnc]> {
159 let DecoderNamespace = "Mips64";
163 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode> {
164 def _D32 : FFR2P<funct, 17, opstr, AFGR64, OpNode>,
165 Requires<[NotFP64bit, HasStdEnc]>;
166 def _D64 : FFR2P<funct, 17, opstr, FGR64, OpNode>,
167 Requires<[IsFP64bit, HasStdEnc]> {
168 let DecoderNamespace = "Mips64";
172 // FP madd/msub/nmadd/nmsub instruction classes.
173 class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
174 SDNode OpNode, RegisterClass RC> :
175 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
176 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
177 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>;
179 class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr,
180 SDNode OpNode, RegisterClass RC> :
181 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
182 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
183 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>;
185 class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
186 SDPatternOperator OpNode= null_frag> :
187 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
188 !strconcat(opstr, "\t$fd, $fs, $ft"),
189 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
190 let isCommutable = IsComm;
193 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
194 SDPatternOperator OpNode = null_frag> {
195 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
196 Requires<[NotFP64bit, HasStdEnc]>;
197 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
198 Requires<[IsFP64bit, HasStdEnc]> {
199 string DecoderNamespace = "Mips64";
203 class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
204 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
205 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
206 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>;
208 multiclass ABSS_M<string opstr, InstrItinClass Itin,
209 SDPatternOperator OpNode= null_frag> {
210 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
211 Requires<[NotFP64bit, HasStdEnc]>;
212 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
213 Requires<[IsFP64bit, HasStdEnc]> {
214 string DecoderNamespace = "Mips64";
218 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
219 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
220 Requires<[NotFP64bit, HasStdEnc]>;
221 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
222 Requires<[IsFP64bit, HasStdEnc]> {
223 let DecoderNamespace = "Mips64";
227 class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
228 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
229 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
230 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
232 class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
233 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
234 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
235 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
238 //===----------------------------------------------------------------------===//
239 // Floating Point Instructions
240 //===----------------------------------------------------------------------===//
241 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
242 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
243 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
244 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
245 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>,
248 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
249 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
250 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
251 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
252 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>,
255 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
256 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
257 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
259 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
260 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
262 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
263 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
264 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
265 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
269 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
270 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>,
272 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>,
275 let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in {
276 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
277 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
278 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
281 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64",
282 neverHasSideEffects = 1 in {
283 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
284 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
285 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
286 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
287 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
290 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
291 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
292 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
293 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
294 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
297 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
299 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
301 // The odd-numbered registers are only referenced when doing loads,
302 // stores, and moves between floating-point and integer registers.
303 // When defining instructions, we reference all 32-bit registers,
304 // regardless of register aliasing.
306 class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
307 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
313 /// Move Control Registers From/To CPU Registers
314 def CFC1 : MFC1_FT<"cfc1", CPURegs, CCR, IIFmove>, MFC1_FM<2>;
315 def CTC1 : MTC1_FT<"ctc1", CCR, CPURegs, IIFmove>, MFC1_FM<6>;
316 def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
317 def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
318 def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
319 def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
321 def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
322 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
323 Requires<[NotFP64bit, HasStdEnc]>;
324 def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
325 Requires<[IsFP64bit, HasStdEnc]> {
326 let DecoderNamespace = "Mips64";
329 /// Floating Point Memory Instructions
330 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
331 def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>;
332 def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>;
333 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
334 let isCodeGenOnly =1;
336 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> {
337 let isCodeGenOnly =1;
341 let Predicates = [NotN64, HasStdEnc] in {
342 def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>;
343 def SWC1 : FPStore<0x39, "swc1", FGR32, mem>;
346 let Predicates = [NotN64, HasMips64, HasStdEnc],
347 DecoderNamespace = "Mips64" in {
348 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
349 def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
352 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
353 def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>;
354 def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>;
357 // Indexed loads and stores.
358 let Predicates = [HasFPIdx, HasStdEnc] in {
359 def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load>;
360 def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store>;
363 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
364 def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load>;
365 def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store>;
368 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
369 def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load>;
370 def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store>;
374 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
375 def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load>;
376 def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load>;
377 def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store>;
378 def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store>;
381 // Load/store doubleword indexed unaligned.
382 let Predicates = [NotMips64, HasStdEnc] in {
383 def LUXC1 : FPIdxLoad<0x5, "luxc1", AFGR64, CPURegs>;
384 def SUXC1 : FPIdxStore<0xd, "suxc1", AFGR64, CPURegs>;
387 let Predicates = [HasMips64, HasStdEnc],
388 DecoderNamespace="Mips64" in {
389 def LUXC164 : FPIdxLoad<0x5, "luxc1", FGR64, CPURegs>;
390 def SUXC164 : FPIdxStore<0xd, "suxc1", FGR64, CPURegs>;
393 /// Floating-point Aritmetic
394 def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
395 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
396 def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
397 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
398 def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
399 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
400 def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
401 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
403 let Predicates = [HasMips32r2, HasStdEnc] in {
404 def MADD_S : FMADDSUB<0x4, 0, "madd.s", fadd, FGR32>;
405 def MSUB_S : FMADDSUB<0x5, 0, "msub.s", fsub, FGR32>;
408 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
409 def NMADD_S : FNMADDSUB<0x6, 0, "nmadd.s", fadd, FGR32>;
410 def NMSUB_S : FNMADDSUB<0x7, 0, "nmsub.s", fsub, FGR32>;
413 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
414 def MADD_D32 : FMADDSUB<0x4, 1, "madd.d", fadd, AFGR64>;
415 def MSUB_D32 : FMADDSUB<0x5, 1, "msub.d", fsub, AFGR64>;
418 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
419 def NMADD_D32 : FNMADDSUB<0x6, 1, "nmadd.d", fadd, AFGR64>;
420 def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub.d", fsub, AFGR64>;
423 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
424 def MADD_D64 : FMADDSUB<0x4, 1, "madd.d", fadd, FGR64>;
425 def MSUB_D64 : FMADDSUB<0x5, 1, "msub.d", fsub, FGR64>;
428 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
430 def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd.d", fadd, FGR64>;
431 def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub.d", fsub, FGR64>;
434 //===----------------------------------------------------------------------===//
435 // Floating Point Branch Codes
436 //===----------------------------------------------------------------------===//
437 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
438 // They must be kept in synch.
439 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
440 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
442 /// Floating Point Branch of False/True (Likely)
443 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
444 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
445 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
446 [(MipsFPBrcond op, bb:$dst)]> {
452 let DecoderMethod = "DecodeBC1" in {
453 def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
454 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
456 //===----------------------------------------------------------------------===//
457 // Floating Point Flag Conditions
458 //===----------------------------------------------------------------------===//
459 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
460 // They must be kept in synch.
461 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
462 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
463 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
464 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
465 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
466 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
467 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
468 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
469 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
470 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
471 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
472 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
473 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
474 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
475 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
476 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
478 class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
479 FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
480 !strconcat("c.$cc.", typestr, "\t$fs, $ft"),
481 [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
483 /// Floating Point Compare
484 let Defs=[FCR31] in {
485 def FCMP_S32 : FCMP<0x10, FGR32, "s">;
486 def FCMP_D32 : FCMP<0x11, AFGR64, "d">,
487 Requires<[NotFP64bit, HasStdEnc]>;
488 def FCMP_D64 : FCMP<0x11, FGR64, "d">,
489 Requires<[IsFP64bit, HasStdEnc]> {
490 let DecoderNamespace = "Mips64";
494 //===----------------------------------------------------------------------===//
495 // Floating Point Pseudo-Instructions
496 //===----------------------------------------------------------------------===//
497 def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src),
498 "# MOVCCRToCCR", []>;
500 // This pseudo instr gets expanded into 2 mtc1 instrs after register
503 PseudoSE<(outs AFGR64:$dst),
504 (ins CPURegs:$lo, CPURegs:$hi), "",
505 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
507 // This pseudo instr gets expanded into 2 mfc1 instrs after register
509 // if n is 0, lower part of src is extracted.
510 // if n is 1, higher part of src is extracted.
511 def ExtractElementF64 :
512 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "",
513 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
515 //===----------------------------------------------------------------------===//
516 // Floating Point Patterns
517 //===----------------------------------------------------------------------===//
518 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
519 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
521 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
522 def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
524 let Predicates = [NotFP64bit, HasStdEnc] in {
525 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
526 (CVT_D32_W (MTC1 CPURegs:$src))>;
527 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
528 (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
529 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
530 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
533 let Predicates = [IsFP64bit, HasStdEnc] in {
534 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
535 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
537 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
538 (CVT_D64_W (MTC1 CPURegs:$src))>;
539 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
540 (CVT_S_L (DMTC1 CPU64Regs:$src))>;
541 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
542 (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
544 def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
545 (MFC1 (TRUNC_W_D64 FGR64:$src))>;
546 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
547 def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
548 (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
550 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
551 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;