1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">;
58 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">;
59 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
60 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
62 // FP immediate patterns.
63 def fpimm0 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(+0.0);
67 def fpimm0neg : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(-0.0);
71 //===----------------------------------------------------------------------===//
72 // Instruction Class Templates
74 // A set of multiclasses is used to address the register usage.
76 // S32 - single precision in 16 32bit even fp registers
77 // single precision in 32 32bit fp registers in SingleOnly mode
78 // S64 - single precision in 32 64bit fp registers (In64BitMode)
79 // D32 - double precision in 16 32bit even fp registers
80 // D64 - double precision in 32 64bit fp registers (In64BitMode)
82 // Only S32 and D32 are supported right now.
83 //===----------------------------------------------------------------------===//
86 class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
87 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
88 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load_a addr:$addr))],
92 class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
93 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
94 !strconcat(opstr, "\t$ft, $addr"), [(store_a RC:$ft, addr:$addr)],
98 class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
99 RegisterClass PRC, PatFrag FOp>:
100 FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
101 !strconcat(opstr, "\t$fd, $index($base)"),
102 [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
107 class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
108 RegisterClass PRC, PatFrag FOp>:
109 FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
110 !strconcat(opstr, "\t$fs, $index($base)"),
111 [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
115 // Instructions that convert an FP value to 32-bit fixed point.
116 multiclass FFR1_W_M<bits<6> funct, string opstr> {
117 def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
118 def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
119 Requires<[NotFP64bit]>;
120 def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
121 Requires<[IsFP64bit]>;
124 // Instructions that convert an FP value to 64-bit fixed point.
125 let Predicates = [IsFP64bit] in
126 multiclass FFR1_L_M<bits<6> funct, string opstr> {
127 def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
128 def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
131 // FP-to-FP conversion instructions.
132 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
133 def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
134 def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
135 Requires<[NotFP64bit]>;
136 def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
137 Requires<[IsFP64bit]>;
140 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
141 let isCommutable = isComm in {
142 def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
143 def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
144 Requires<[NotFP64bit]>;
145 def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
146 Requires<[IsFP64bit]>;
150 // FP madd/msub/nmadd/nmsub instruction classes.
151 class FMADDSUB<bits<3> funct, bits<3> fmt, string opstr, string fmtstr,
152 SDNode OpNode, RegisterClass RC> :
153 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
154 !strconcat(opstr, ".", fmtstr, "\t$fd, $fr, $fs, $ft"),
155 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))]>;
157 class FNMADDSUB<bits<3> funct, bits<3> fmt, string opstr, string fmtstr,
158 SDNode OpNode, RegisterClass RC> :
159 FFMADDSUB<funct, fmt, (outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
160 !strconcat(opstr, ".", fmtstr, "\t$fd, $fr, $fs, $ft"),
161 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))]>;
163 //===----------------------------------------------------------------------===//
164 // Floating Point Instructions
165 //===----------------------------------------------------------------------===//
166 defm ROUND_W : FFR1_W_M<0xc, "round">;
167 defm ROUND_L : FFR1_L_M<0x8, "round">;
168 defm TRUNC_W : FFR1_W_M<0xd, "trunc">;
169 defm TRUNC_L : FFR1_L_M<0x9, "trunc">;
170 defm CEIL_W : FFR1_W_M<0xe, "ceil">;
171 defm CEIL_L : FFR1_L_M<0xa, "ceil">;
172 defm FLOOR_W : FFR1_W_M<0xf, "floor">;
173 defm FLOOR_L : FFR1_L_M<0xb, "floor">;
174 defm CVT_W : FFR1_W_M<0x24, "cvt">;
175 defm CVT_L : FFR1_L_M<0x25, "cvt">;
177 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
179 let Predicates = [NotFP64bit] in {
180 def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
181 def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
182 def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
185 let Predicates = [IsFP64bit] in {
186 def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
187 def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
188 def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
189 def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>;
190 def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
193 let Predicates = [NoNaNsFPMath] in
194 defm FABS : FFR1P_M<0x5, "abs", fabs>;
195 defm FNEG : FFR1P_M<0x7, "neg", fneg>;
196 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
198 // The odd-numbered registers are only referenced when doing loads,
199 // stores, and moves between floating-point and integer registers.
200 // When defining instructions, we reference all 32-bit registers,
201 // regardless of register aliasing.
203 class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
204 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
210 /// Move Control Registers From/To CPU Registers
211 def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
212 "cfc1\t$rt, $fs", []>;
214 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
215 "ctc1\t$rt, $fs", []>;
217 def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
219 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
221 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
223 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
225 def DMFC1 : FFRGPR<0x01, (outs CPU64Regs:$rt), (ins FGR64:$fs),
227 [(set CPU64Regs:$rt, (bitconvert FGR64:$fs))]>;
229 def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt),
231 [(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>;
233 def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
234 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
235 Requires<[NotFP64bit]>;
236 def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
237 Requires<[IsFP64bit]>;
239 /// Floating Point Memory Instructions
240 let Predicates = [IsN64] in {
241 def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>;
242 def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>;
243 def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64>;
244 def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64>;
247 let Predicates = [NotN64] in {
248 def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>;
249 def SWC1 : FPStore<0x39, "swc1", FGR32, mem>;
252 let Predicates = [NotN64, HasMips64] in {
253 def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
254 def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
257 let Predicates = [NotN64, NotMips64] in {
258 def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>;
259 def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>;
262 // Indexed loads and stores.
263 let Predicates = [HasMips32r2Or64] in {
264 def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load_a>;
265 def LUXC1 : FPIdxLoad<0x5, "luxc1", FGR32, CPURegs, load_u>;
266 def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store_a>;
267 def SUXC1 : FPIdxStore<0xd, "suxc1", FGR32, CPURegs, store_u>;
270 let Predicates = [HasMips32r2, NotMips64] in {
271 def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load_a>;
272 def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>;
275 let Predicates = [HasMips64, NotN64] in {
276 def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>;
277 def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>;
281 let Predicates = [IsN64] in {
282 def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
283 def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>;
284 def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
285 def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store_a>;
286 def SUXC1_P8 : FPIdxStore<0xd, "suxc1", FGR32, CPU64Regs, store_u>;
287 def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store_a>;
290 /// Floating-point Aritmetic
291 defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
292 defm FDIV : FFR2P_M<0x03, "div", fdiv>;
293 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
294 defm FSUB : FFR2P_M<0x01, "sub", fsub>;
296 let Predicates = [HasMips32r2] in {
297 def MADD_S : FMADDSUB<0x4, 0, "madd", "s", fadd, FGR32>;
298 def MSUB_S : FMADDSUB<0x5, 0, "msub", "s", fsub, FGR32>;
301 let Predicates = [HasMips32r2, NoNaNsFPMath] in {
302 def NMADD_S : FNMADDSUB<0x6, 0, "nmadd", "s", fadd, FGR32>;
303 def NMSUB_S : FNMADDSUB<0x7, 0, "nmsub", "s", fsub, FGR32>;
306 let Predicates = [HasMips32r2, NotFP64bit] in {
307 def MADD_D32 : FMADDSUB<0x4, 1, "madd", "d", fadd, AFGR64>;
308 def MSUB_D32 : FMADDSUB<0x5, 1, "msub", "d", fsub, AFGR64>;
311 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath] in {
312 def NMADD_D32 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, AFGR64>;
313 def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, AFGR64>;
316 let Predicates = [HasMips32r2, IsFP64bit] in {
317 def MADD_D64 : FMADDSUB<0x4, 1, "madd", "d", fadd, FGR64>;
318 def MSUB_D64 : FMADDSUB<0x5, 1, "msub", "d", fsub, FGR64>;
321 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath] in {
322 def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, FGR64>;
323 def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, FGR64>;
326 //===----------------------------------------------------------------------===//
327 // Floating Point Branch Codes
328 //===----------------------------------------------------------------------===//
329 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
330 // They must be kept in synch.
331 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
332 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
334 /// Floating Point Branch of False/True (Likely)
335 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
336 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
337 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
338 [(MipsFPBrcond op, bb:$dst)]> {
344 def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
345 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
347 //===----------------------------------------------------------------------===//
348 // Floating Point Flag Conditions
349 //===----------------------------------------------------------------------===//
350 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
351 // They must be kept in synch.
352 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
353 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
354 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
355 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
356 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
357 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
358 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
359 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
360 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
361 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
362 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
363 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
364 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
365 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
366 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
367 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
369 class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
370 FCC<fmt, (outs), (ins RC:$fs, RC:$ft, condcode:$cc),
371 !strconcat("c.$cc.", typestr, "\t$fs, $ft"),
372 [(MipsFPCmp RC:$fs, RC:$ft, imm:$cc)]>;
374 /// Floating Point Compare
375 let Defs=[FCR31] in {
376 def FCMP_S32 : FCMP<0x10, FGR32, "s">;
377 def FCMP_D32 : FCMP<0x11, AFGR64, "d">, Requires<[NotFP64bit]>;
378 def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]>;
381 //===----------------------------------------------------------------------===//
382 // Floating Point Pseudo-Instructions
383 //===----------------------------------------------------------------------===//
384 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
385 "# MOVCCRToCCR", []>;
387 // This pseudo instr gets expanded into 2 mtc1 instrs after register
390 MipsPseudo<(outs AFGR64:$dst),
391 (ins CPURegs:$lo, CPURegs:$hi), "",
392 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
394 // This pseudo instr gets expanded into 2 mfc1 instrs after register
396 // if n is 0, lower part of src is extracted.
397 // if n is 1, higher part of src is extracted.
398 def ExtractElementF64 :
399 MipsPseudo<(outs CPURegs:$dst),
400 (ins AFGR64:$src, i32imm:$n), "",
402 (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
404 //===----------------------------------------------------------------------===//
405 // Floating Point Patterns
406 //===----------------------------------------------------------------------===//
407 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
408 def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
410 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
411 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
413 let Predicates = [NotFP64bit] in {
414 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
415 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
416 def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
417 def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
420 let Predicates = [IsFP64bit] in {
421 def : Pat<(f64 fpimm0), (DMTC1 ZERO_64)>;
422 def : Pat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
424 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D64_W (MTC1 CPURegs:$src))>;
425 def : Pat<(f32 (sint_to_fp CPU64Regs:$src)),
426 (CVT_S_L (DMTC1 CPU64Regs:$src))>;
427 def : Pat<(f64 (sint_to_fp CPU64Regs:$src)),
428 (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
430 def : Pat<(i32 (fp_to_sint FGR64:$src)), (MFC1 (TRUNC_W_D64 FGR64:$src))>;
431 def : Pat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
432 def : Pat<(i64 (fp_to_sint FGR64:$src)), (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
434 def : Pat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
435 def : Pat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
438 // Patterns for unaligned floating point loads and stores.
439 let Predicates = [HasMips32r2Or64, NotN64] in {
440 def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
441 def : Pat<(store_u FGR32:$src, CPURegs:$addr),
442 (SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
445 let Predicates = [IsN64] in {
446 def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
447 def : Pat<(store_u FGR32:$src, CPU64Regs:$addr),
448 (SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;