1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
44 [SDNPHasChain, SDNPOptInGlue]>;
45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
47 SDT_MipsExtractElementF64>;
49 // Operand for printing out a condition code.
50 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
51 def condcode : Operand<i32>;
53 //===----------------------------------------------------------------------===//
54 // Feature predicates.
55 //===----------------------------------------------------------------------===//
57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
58 AssemblerPredicate<"FeatureFP64Bit">;
59 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
60 AssemblerPredicate<"!FeatureFP64Bit">;
61 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
62 AssemblerPredicate<"FeatureSingleFloat">;
63 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
64 AssemblerPredicate<"!FeatureSingleFloat">;
66 // FP immediate patterns.
67 def fpimm0 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+0.0);
71 def fpimm0neg : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-0.0);
75 //===----------------------------------------------------------------------===//
76 // Instruction Class Templates
78 // A set of multiclasses is used to address the register usage.
80 // S32 - single precision in 16 32bit even fp registers
81 // single precision in 32 32bit fp registers in SingleOnly mode
82 // S64 - single precision in 32 64bit fp registers (In64BitMode)
83 // D32 - double precision in 16 32bit even fp registers
84 // D64 - double precision in 32 64bit fp registers (In64BitMode)
86 // Only S32 and D32 are supported right now.
87 //===----------------------------------------------------------------------===//
89 class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
90 SDPatternOperator OpNode= null_frag> :
91 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
92 !strconcat(opstr, "\t$fd, $fs, $ft"),
93 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
94 let isCommutable = IsComm;
97 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
98 SDPatternOperator OpNode = null_frag> {
99 def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
100 Requires<[NotFP64bit, HasStdEnc]>;
101 def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
102 Requires<[IsFP64bit, HasStdEnc]> {
103 string DecoderNamespace = "Mips64";
107 class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
108 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
109 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
110 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>;
112 multiclass ABSS_M<string opstr, InstrItinClass Itin,
113 SDPatternOperator OpNode= null_frag> {
114 def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
115 Requires<[NotFP64bit, HasStdEnc]>;
116 def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
117 Requires<[IsFP64bit, HasStdEnc]> {
118 string DecoderNamespace = "Mips64";
122 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
123 def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
124 Requires<[NotFP64bit, HasStdEnc]>;
125 def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
126 Requires<[IsFP64bit, HasStdEnc]> {
127 let DecoderNamespace = "Mips64";
131 class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
132 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
133 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
134 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
136 class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
137 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
138 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
139 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
141 class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
142 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
143 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
144 [(set RC:$rt, (OpNode addr:$addr))], Itin, FrmFI> {
145 let DecoderMethod = "DecodeFMem";
148 class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
149 Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
150 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
151 [(OpNode RC:$rt, addr:$addr)], Itin, FrmFI> {
152 let DecoderMethod = "DecodeFMem";
155 class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
156 SDPatternOperator OpNode = null_frag> :
157 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
158 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
159 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
161 class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
162 SDPatternOperator OpNode = null_frag> :
163 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
164 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
165 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
168 class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
169 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
170 InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
171 !strconcat(opstr, "\t$fd, ${index}(${base})"),
172 [(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI>;
174 class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
175 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
176 InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
177 !strconcat(opstr, "\t$fs, ${index}(${base})"),
178 [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>;
180 class BC1F_FT<string opstr, InstrItinClass Itin,
181 SDPatternOperator Op = null_frag> :
182 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
183 [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
185 let isTerminator = 1;
186 let hasDelaySlot = 1;
191 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
192 SDPatternOperator OpNode = null_frag> :
193 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
194 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
195 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
199 //===----------------------------------------------------------------------===//
200 // Floating Point Instructions
201 //===----------------------------------------------------------------------===//
202 def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
203 def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
204 def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
205 def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
206 def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>,
209 defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
210 defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
211 defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
212 defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
213 defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>,
216 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
217 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
218 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
220 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
221 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
223 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
224 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
225 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
226 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
230 def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
231 def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>,
233 def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>,
236 let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in {
237 def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
238 def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
239 def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
242 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64",
243 neverHasSideEffects = 1 in {
244 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
245 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
246 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
247 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
248 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
251 let Predicates = [NoNaNsFPMath, HasStdEnc] in {
252 def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
253 def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
254 defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
255 defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
258 def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
260 defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
262 // The odd-numbered registers are only referenced when doing loads,
263 // stores, and moves between floating-point and integer registers.
264 // When defining instructions, we reference all 32-bit registers,
265 // regardless of register aliasing.
267 /// Move Control Registers From/To CPU Registers
268 def CFC1 : MFC1_FT<"cfc1", CPURegs, CCR, IIFmove>, MFC1_FM<2>;
269 def CTC1 : MTC1_FT<"ctc1", CCR, CPURegs, IIFmove>, MFC1_FM<6>;
270 def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
271 def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
272 def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
273 def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
275 def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
276 def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
277 Requires<[NotFP64bit, HasStdEnc]>;
278 def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
279 Requires<[IsFP64bit, HasStdEnc]> {
280 let DecoderNamespace = "Mips64";
283 /// Floating Point Memory Instructions
284 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
285 def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
286 def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
287 def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
288 let isCodeGenOnly =1;
290 def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
291 let isCodeGenOnly =1;
295 let Predicates = [NotN64, HasStdEnc] in {
296 def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
297 def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
300 let Predicates = [NotN64, HasMips64, HasStdEnc],
301 DecoderNamespace = "Mips64" in {
302 def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
303 def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
306 let Predicates = [NotN64, NotMips64, HasStdEnc] in {
307 def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem, load>, LW_FM<0x35>;
308 def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem, store>, LW_FM<0x3d>;
311 // Indexed loads and stores.
312 let Predicates = [HasFPIdx, HasStdEnc] in {
313 def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
314 def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
317 let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
318 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
319 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
322 let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
323 def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
324 def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
328 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
329 def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
330 def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
332 def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
334 def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
338 // Load/store doubleword indexed unaligned.
339 let Predicates = [NotMips64, HasStdEnc] in {
340 def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
341 def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
344 let Predicates = [HasMips64, HasStdEnc],
345 DecoderNamespace="Mips64" in {
346 def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
347 def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
350 /// Floating-point Aritmetic
351 def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
352 defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
353 def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
354 defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
355 def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
356 defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
357 def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
358 defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
360 let Predicates = [HasMips32r2, HasStdEnc] in {
361 def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
362 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
365 let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
366 def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
367 def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
370 let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
371 def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
372 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
375 let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
376 def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
378 def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
382 let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
383 def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
384 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
387 let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
389 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
391 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
395 //===----------------------------------------------------------------------===//
396 // Floating Point Branch Codes
397 //===----------------------------------------------------------------------===//
398 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
399 // They must be kept in synch.
400 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
401 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
403 let DecoderMethod = "DecodeBC1" in {
404 def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
405 def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
407 //===----------------------------------------------------------------------===//
408 // Floating Point Flag Conditions
409 //===----------------------------------------------------------------------===//
410 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
411 // They must be kept in synch.
412 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
413 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
414 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
415 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
416 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
417 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
418 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
419 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
420 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
421 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
422 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
423 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
424 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
425 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
426 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
427 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
429 /// Floating Point Compare
430 def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
431 def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
432 Requires<[NotFP64bit, HasStdEnc]>;
433 let DecoderNamespace = "Mips64" in
434 def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
435 Requires<[IsFP64bit, HasStdEnc]>;
437 //===----------------------------------------------------------------------===//
438 // Floating Point Pseudo-Instructions
439 //===----------------------------------------------------------------------===//
440 def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCR:$src),
441 "# MOVCCRToCCR", []>;
443 // This pseudo instr gets expanded into 2 mtc1 instrs after register
446 PseudoSE<(outs AFGR64:$dst),
447 (ins CPURegs:$lo, CPURegs:$hi), "",
448 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
450 // This pseudo instr gets expanded into 2 mfc1 instrs after register
452 // if n is 0, lower part of src is extracted.
453 // if n is 1, higher part of src is extracted.
454 def ExtractElementF64 :
455 PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n), "",
456 [(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
458 //===----------------------------------------------------------------------===//
459 // Floating Point Patterns
460 //===----------------------------------------------------------------------===//
461 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
462 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
464 def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
465 def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
467 let Predicates = [NotFP64bit, HasStdEnc] in {
468 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
469 (CVT_D32_W (MTC1 CPURegs:$src))>;
470 def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
471 (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
472 def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
473 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
476 let Predicates = [IsFP64bit, HasStdEnc] in {
477 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
478 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
480 def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
481 (CVT_D64_W (MTC1 CPURegs:$src))>;
482 def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
483 (CVT_S_L (DMTC1 CPU64Regs:$src))>;
484 def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
485 (CVT_D64_L (DMTC1 CPU64Regs:$src))>;
487 def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
488 (MFC1 (TRUNC_W_D64 FGR64:$src))>;
489 def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
490 def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
491 (DMFC1 (TRUNC_L_D64 FGR64:$src))>;
493 def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
494 def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;