1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Mips FPU instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
42 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
43 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
44 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
45 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
46 [SDNPHasChain, SDNPOptInGlue]>;
47 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
48 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
49 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
50 SDT_MipsExtractElementF64>;
52 // Operand for printing out a condition code.
53 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
54 def condcode : Operand<i32>;
56 //===----------------------------------------------------------------------===//
57 // Feature predicates.
58 //===----------------------------------------------------------------------===//
60 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
61 AssemblerPredicate<"FeatureFP64Bit">;
62 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
63 AssemblerPredicate<"!FeatureFP64Bit">;
64 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
65 AssemblerPredicate<"FeatureSingleFloat">;
66 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
67 AssemblerPredicate<"!FeatureSingleFloat">;
69 //===----------------------------------------------------------------------===//
70 // Mips FGR size adjectives.
71 // They are mutually exclusive.
72 //===----------------------------------------------------------------------===//
74 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
75 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
77 //===----------------------------------------------------------------------===//
79 // FP immediate patterns.
80 def fpimm0 : PatLeaf<(fpimm), [{
81 return N->isExactlyValue(+0.0);
84 def fpimm0neg : PatLeaf<(fpimm), [{
85 return N->isExactlyValue(-0.0);
88 //===----------------------------------------------------------------------===//
89 // Instruction Class Templates
91 // A set of multiclasses is used to address the register usage.
93 // S32 - single precision in 16 32bit even fp registers
94 // single precision in 32 32bit fp registers in SingleOnly mode
95 // S64 - single precision in 32 64bit fp registers (In64BitMode)
96 // D32 - double precision in 16 32bit even fp registers
97 // D64 - double precision in 32 64bit fp registers (In64BitMode)
99 // Only S32 and D32 are supported right now.
100 //===----------------------------------------------------------------------===//
102 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
103 SDPatternOperator OpNode= null_frag> :
104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
105 !strconcat(opstr, "\t$fd, $fs, $ft"),
106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> {
107 let isCommutable = IsComm;
110 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
111 SDPatternOperator OpNode = null_frag> {
112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
113 AdditionalRequires<[NotFP64bit]>;
114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
116 AdditionalRequires<[IsFP64bit]> {
117 string DecoderNamespace = "Mips64";
121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
127 multiclass ABSS_M<string opstr, InstrItinClass Itin,
128 SDPatternOperator OpNode= null_frag> {
129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
130 AdditionalRequires<[NotFP64bit]>;
131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
132 AdditionalRequires<[IsFP64bit]> {
133 string DecoderNamespace = "Mips64";
137 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
139 AdditionalRequires<[NotFP64bit]>;
140 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
141 AdditionalRequires<[IsFP64bit]> {
142 let DecoderNamespace = "Mips64";
146 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
147 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
151 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
152 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
156 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
157 InstrItinClass Itin> :
158 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
159 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> {
160 // $fs_in is part of a white lie to work around a widespread bug in the FPU
161 // implementation. See expandBuildPairF64 for details.
162 let Constraints = "$fs = $fs_in";
165 class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
166 SDPatternOperator OpNode= null_frag> :
167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
169 let DecoderMethod = "DecodeFMem";
173 class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
174 SDPatternOperator OpNode= null_frag> :
175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
177 let DecoderMethod = "DecodeFMem";
181 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
182 SDPatternOperator OpNode= null_frag> :
183 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
184 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
185 let DecoderMethod = "DecodeFMem2";
189 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
190 SDPatternOperator OpNode= null_frag> :
191 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
192 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
193 let DecoderMethod = "DecodeFMem2";
197 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
198 SDPatternOperator OpNode= null_frag> :
199 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
200 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
201 let DecoderMethod = "DecodeFMem3";
205 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
206 SDPatternOperator OpNode= null_frag> :
207 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
208 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
209 let DecoderMethod = "DecodeFMem3";
213 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
214 SDPatternOperator OpNode = null_frag> :
215 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
216 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
217 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
220 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
221 SDPatternOperator OpNode = null_frag> :
222 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
223 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
224 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
227 class LWXC1_FT<string opstr, RegisterOperand DRC,
228 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
229 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
230 !strconcat(opstr, "\t$fd, ${index}(${base})"),
231 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
233 let AddedComplexity = 20;
236 class SWXC1_FT<string opstr, RegisterOperand DRC,
237 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
238 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
239 !strconcat(opstr, "\t$fs, ${index}(${base})"),
240 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
242 let AddedComplexity = 20;
245 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
246 SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
247 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
248 !strconcat(opstr, "\t$fcc, $offset"),
249 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
252 let isTerminator = 1;
253 let hasDelaySlot = DelaySlot;
257 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
258 SDPatternOperator OpNode = null_frag> :
259 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
260 !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
261 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
262 !strconcat("c.$cond.", typestr)> {
264 let isCodeGenOnly = 1;
267 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
268 InstrItinClass itin> :
269 InstSE<(outs), (ins RC:$fs, RC:$ft),
270 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin,
273 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
274 InstrItinClass itin> {
275 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
276 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
277 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
278 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>;
279 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>;
280 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>;
281 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>;
282 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>;
283 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>;
284 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>;
285 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>;
286 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>;
287 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>;
288 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>;
289 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>;
290 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
293 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
294 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
295 AdditionalRequires<[NotFP64bit]>;
296 let DecoderNamespace = "Mips64" in
297 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
298 AdditionalRequires<[IsFP64bit]>;
300 //===----------------------------------------------------------------------===//
301 // Floating Point Instructions
302 //===----------------------------------------------------------------------===//
303 def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
304 ABSS_FM<0xc, 16>, ISA_MIPS2;
305 def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
306 ABSS_FM<0xd, 16>, ISA_MIPS2;
307 def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
308 ABSS_FM<0xe, 16>, ISA_MIPS2;
309 def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
310 ABSS_FM<0xf, 16>, ISA_MIPS2;
311 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
314 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
315 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
316 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
317 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
318 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
320 let DecoderNamespace = "Mips64" in {
321 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
322 ABSS_FM<0x8, 16>, FGR_64;
323 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
324 ABSS_FM<0x8, 17>, FGR_64;
325 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
326 ABSS_FM<0x9, 16>, FGR_64;
327 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
328 ABSS_FM<0x9, 17>, FGR_64;
329 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
330 ABSS_FM<0xa, 16>, FGR_64;
331 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
332 ABSS_FM<0xa, 17>, FGR_64;
333 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
334 ABSS_FM<0xb, 16>, FGR_64;
335 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
336 ABSS_FM<0xb, 17>, FGR_64;
339 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
341 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
342 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
343 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
344 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
346 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
347 ABSS_FM<0x20, 17>, FGR_32;
348 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
349 ABSS_FM<0x21, 20>, FGR_32;
350 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
351 ABSS_FM<0x21, 16>, FGR_32;
353 let DecoderNamespace = "Mips64" in {
354 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
355 ABSS_FM<0x20, 17>, FGR_64;
356 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
357 ABSS_FM<0x20, 21>, FGR_64;
358 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
359 ABSS_FM<0x21, 20>, FGR_64;
360 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
361 ABSS_FM<0x21, 16>, FGR_64;
362 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
363 ABSS_FM<0x21, 21>, FGR_64;
366 let isPseudo = 1, isCodeGenOnly = 1 in {
367 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
368 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
369 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
370 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
371 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
374 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
376 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
378 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
379 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
381 def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>,
382 ABSS_FM<0x4, 16>, ISA_MIPS2;
383 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
385 // The odd-numbered registers are only referenced when doing loads,
386 // stores, and moves between floating-point and integer registers.
387 // When defining instructions, we reference all 32-bit registers,
388 // regardless of register aliasing.
390 /// Move Control Registers From/To CPU Registers
391 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
392 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
393 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
394 bitconvert>, MFC1_FM<0>;
395 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
396 bitconvert>, MFC1_FM<4>;
397 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
398 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
399 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
400 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
401 let DecoderNamespace = "Mips64";
403 def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
404 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
405 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
406 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
407 let DecoderNamespace = "Mips64";
409 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
410 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
411 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
412 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
414 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
416 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
417 ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>;
418 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
419 ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> {
420 let DecoderNamespace = "Mips64";
423 /// Floating Point Memory Instructions
424 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
425 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
427 let DecoderNamespace = "Mips64" in {
428 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
430 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
434 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
436 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
439 // Cop2 Memory Instructions
440 // FIXME: These aren't really FPU instructions and as such don't belong in this
442 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
443 ISA_MIPS1_NOT_32R6_64R6;
444 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
445 ISA_MIPS1_NOT_32R6_64R6;
446 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
447 ISA_MIPS2_NOT_32R6_64R6;
448 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
449 ISA_MIPS2_NOT_32R6_64R6;
451 // Cop3 Memory Instructions
452 // FIXME: These aren't really FPU instructions and as such don't belong in this
454 let DecoderNamespace = "COP3_" in {
455 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
456 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
457 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
459 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
463 // Indexed loads and stores.
464 // Base register + offset register addressing mode (indicated by "x" in the
465 // instruction mnemonic) is disallowed under NaCl.
466 let AdditionalPredicates = [IsNotNaCl] in {
467 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
468 INSN_MIPS4_32R2_NOT_32R6_64R6;
469 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
470 INSN_MIPS4_32R2_NOT_32R6_64R6;
473 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
474 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
475 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
476 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
477 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
480 let DecoderNamespace="Mips64" in {
481 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
482 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
483 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
484 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
487 // Load/store doubleword indexed unaligned.
488 let AdditionalPredicates = [IsNotNaCl] in {
489 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
490 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
491 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
492 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
495 let DecoderNamespace="Mips64" in {
496 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
497 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
498 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
499 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
502 /// Floating-point Aritmetic
503 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
505 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
506 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
508 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
509 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
511 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
512 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
514 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
516 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
517 MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
518 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
519 MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
521 let AdditionalPredicates = [NoNaNsFPMath] in {
522 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
523 MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
524 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
525 MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
528 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
529 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
530 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
531 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
533 let AdditionalPredicates = [NoNaNsFPMath] in {
534 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
535 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
536 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
537 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
540 let isCodeGenOnly=1 in {
541 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
542 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
543 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
544 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
547 let AdditionalPredicates = [NoNaNsFPMath],
549 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
550 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
551 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
552 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
555 //===----------------------------------------------------------------------===//
556 // Floating Point Branch Codes
557 //===----------------------------------------------------------------------===//
558 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
559 // They must be kept in synch.
560 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
561 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
563 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>,
564 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
565 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>,
566 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
567 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>,
568 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
569 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>,
570 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
572 //===----------------------------------------------------------------------===//
573 // Floating Point Flag Conditions
574 //===----------------------------------------------------------------------===//
575 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
576 // They must be kept in synch.
577 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
578 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
579 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
580 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
581 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
582 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
583 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
584 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
585 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
586 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
587 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
588 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
589 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
590 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
591 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
592 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
594 /// Floating Point Compare
595 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
596 ISA_MIPS1_NOT_32R6_64R6;
597 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
598 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[NotFP64bit]>;
599 let DecoderNamespace = "Mips64" in
600 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
601 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>;
603 //===----------------------------------------------------------------------===//
604 // Floating Point Pseudo-Instructions
605 //===----------------------------------------------------------------------===//
607 // This pseudo instr gets expanded into 2 mtc1 instrs after register
609 class BuildPairF64Base<RegisterOperand RO> :
610 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
611 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
613 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
614 AdditionalRequires<[NotFP64bit]>;
615 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
616 AdditionalRequires<[IsFP64bit]>;
618 // This pseudo instr gets expanded into 2 mfc1 instrs after register
620 // if n is 0, lower part of src is extracted.
621 // if n is 1, higher part of src is extracted.
622 class ExtractElementF64Base<RegisterOperand RO> :
623 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
624 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
626 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
627 AdditionalRequires<[NotFP64bit]>;
628 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
629 AdditionalRequires<[IsFP64bit]>;
631 //===----------------------------------------------------------------------===//
633 //===----------------------------------------------------------------------===//
634 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
635 ISA_MIPS1_NOT_32R6_64R6;
636 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
637 ISA_MIPS2_NOT_32R6_64R6;
638 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
639 ISA_MIPS1_NOT_32R6_64R6;
640 def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
641 ISA_MIPS2_NOT_32R6_64R6;
643 //===----------------------------------------------------------------------===//
644 // Floating Point Patterns
645 //===----------------------------------------------------------------------===//
646 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
647 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
649 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
650 (PseudoCVT_S_W GPR32Opnd:$src)>;
651 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
652 (TRUNC_W_S FGR32Opnd:$src)>;
654 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
655 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
656 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
657 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
658 def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
659 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
660 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
661 (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
663 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
664 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
666 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
667 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
668 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
669 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
670 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
671 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
673 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
674 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
675 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
676 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
677 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
678 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
680 def : MipsPat<(f32 (fround FGR64Opnd:$src)),
681 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
682 def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
683 (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
685 // Patterns for loads/stores with a reg+imm operand.
686 let AddedComplexity = 40 in {
687 def : LoadRegImmPat<LWC1, f32, load>;
688 def : StoreRegImmPat<SWC1, f32>;
690 def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
691 def : StoreRegImmPat<SDC164, f64>, FGR_64;
693 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
694 def : StoreRegImmPat<SDC1, f64>, FGR_32;