1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
55 def Std2MicroMipsR6 : InstrMapping {
56 let FilterClass = "StdMMR6Rel";
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
59 // Instructions with the same predicate sense form a column.
60 let ColFields = ["Arch"];
61 // The key column is the unpredicated instructions.
63 // Value columns are PredSense=true and PredSense=false
64 let ValueCols = [["se"], ["micromipsr6"]];
71 // Generic Mips Format
72 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
73 InstrItinClass itin, Format f>: Instruction
78 let Namespace = "Mips";
84 // Top 6 bits are the 'opcode' field
85 let Inst{31-26} = Opcode;
87 let OutOperandList = outs;
88 let InOperandList = ins;
90 let AsmString = asmstr;
91 let Pattern = pattern;
95 // Attributes specific to Mips instructions...
97 bits<4> FormBits = Form.Value;
99 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
100 let TSFlags{3-0} = FormBits;
102 let DecoderNamespace = "Mips";
104 field bits<32> SoftFail = 0;
107 // Mips32/64 Instruction Format
108 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
109 InstrItinClass itin, Format f, string opstr = ""> :
110 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
111 let EncodingPredicates = [HasStdEnc];
112 string BaseOpcode = opstr;
116 // Mips Pseudo Instructions Format
117 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
118 InstrItinClass itin = IIPseudo> :
119 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
120 let isCodeGenOnly = 1;
124 // Mips32/64 Pseudo Instruction Format
125 class PseudoSE<dag outs, dag ins, list<dag> pattern,
126 InstrItinClass itin = IIPseudo> :
127 MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
128 let EncodingPredicates = [HasStdEnc];
131 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
132 // These are aliases that require C++ handling to convert to the target
133 // instruction, while InstAliases can be handled directly by tblgen.
134 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
135 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
139 //===----------------------------------------------------------------------===//
140 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
141 //===----------------------------------------------------------------------===//
143 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
144 list<dag> pattern, InstrItinClass itin>:
145 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
156 let Inst{25-21} = rs;
157 let Inst{20-16} = rt;
158 let Inst{15-11} = rd;
159 let Inst{10-6} = shamt;
160 let Inst{5-0} = funct;
163 //===----------------------------------------------------------------------===//
164 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
165 //===----------------------------------------------------------------------===//
167 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
168 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
176 let Inst{25-21} = rs;
177 let Inst{20-16} = rt;
178 let Inst{15-0} = imm16;
181 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
182 list<dag> pattern, InstrItinClass itin>:
183 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
191 let Inst{25-21} = rs;
192 let Inst{20-16} = rt;
193 let Inst{15-0} = imm16;
196 //===----------------------------------------------------------------------===//
197 // Format J instruction class in Mips : <|opcode|address|>
198 //===----------------------------------------------------------------------===//
200 class FJ<bits<6> op> : StdArch
206 let Inst{31-26} = op;
207 let Inst{25-0} = target;
210 //===----------------------------------------------------------------------===//
211 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
212 //===----------------------------------------------------------------------===//
213 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
221 let Inst{31-26} = op;
222 let Inst{25-21} = mfmt;
223 let Inst{20-16} = rt;
224 let Inst{15-11} = rd;
229 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
236 let Inst{31-26} = op;
237 let Inst{25-21} = rs;
238 let Inst{20-16} = rt;
239 let Inst{15-11} = rd;
241 let Inst{5-0} = funct;
244 class ADDI_FM<bits<6> op> : StdArch {
251 let Inst{31-26} = op;
252 let Inst{25-21} = rs;
253 let Inst{20-16} = rt;
254 let Inst{15-0} = imm16;
257 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
266 let Inst{21} = rotate;
267 let Inst{20-16} = rt;
268 let Inst{15-11} = rd;
269 let Inst{10-6} = shamt;
270 let Inst{5-0} = funct;
273 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
281 let Inst{25-21} = rs;
282 let Inst{20-16} = rt;
283 let Inst{15-11} = rd;
285 let Inst{6} = rotate;
286 let Inst{5-0} = funct;
289 class BEQ_FM<bits<6> op> : StdArch {
296 let Inst{31-26} = op;
297 let Inst{25-21} = rs;
298 let Inst{20-16} = rt;
299 let Inst{15-0} = offset;
302 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
308 let Inst{31-26} = op;
309 let Inst{25-21} = rs;
310 let Inst{20-16} = funct;
311 let Inst{15-0} = offset;
314 class BBIT_FM<bits<6> op> : StdArch {
321 let Inst{31-26} = op;
322 let Inst{25-21} = rs;
324 let Inst{15-0} = offset;
327 class SLTI_FM<bits<6> op> : StdArch {
334 let Inst{31-26} = op;
335 let Inst{25-21} = rs;
336 let Inst{20-16} = rt;
337 let Inst{15-0} = imm16;
340 class MFLO_FM<bits<6> funct> : StdArch {
347 let Inst{15-11} = rd;
349 let Inst{5-0} = funct;
352 class MTLO_FM<bits<6> funct> : StdArch {
358 let Inst{25-21} = rs;
360 let Inst{5-0} = funct;
363 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
369 let Inst{31-26} = 0x1f;
371 let Inst{20-16} = rt;
372 let Inst{15-11} = rd;
373 let Inst{10-6} = funct;
374 let Inst{5-0} = funct2;
377 class CLO_FM<bits<6> funct> : StdArch {
384 let Inst{31-26} = 0x1c;
385 let Inst{25-21} = rs;
386 let Inst{20-16} = rt;
387 let Inst{15-11} = rd;
389 let Inst{5-0} = funct;
393 class LUI_FM : StdArch {
399 let Inst{31-26} = 0xf;
401 let Inst{20-16} = rt;
402 let Inst{15-0} = imm16;
412 let Inst{25-21} = rs;
414 let Inst{15-11} = rd;
419 class BGEZAL_FM<bits<5> funct> : StdArch {
426 let Inst{25-21} = rs;
427 let Inst{20-16} = funct;
428 let Inst{15-0} = offset;
431 class SYNC_FM : StdArch {
437 let Inst{10-6} = stype;
441 class SYNCI_FM : StdArch {
442 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
444 bits<5> rs = addr{20-16};
445 bits<16> offset = addr{15-0};
449 let Inst{31-26} = 0b000001;
450 let Inst{25-21} = rs;
451 let Inst{20-16} = 0b11111;
452 let Inst{15-0} = offset;
455 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
461 let Inst{31-26} = op;
462 let Inst{25-21} = rs;
463 let Inst{20-16} = rt;
465 let Inst{5-0} = funct;
468 class EXT_FM<bits<6> funct> : StdArch {
476 let Inst{31-26} = 0x1f;
477 let Inst{25-21} = rs;
478 let Inst{20-16} = rt;
479 let Inst{15-11} = size;
480 let Inst{10-6} = pos;
481 let Inst{5-0} = funct;
484 class RDHWR_FM : StdArch {
490 let Inst{31-26} = 0x1f;
492 let Inst{20-16} = rt;
493 let Inst{15-11} = rd;
495 let Inst{5-0} = 0x3b;
498 class TEQ_FM<bits<6> funct> : StdArch {
506 let Inst{25-21} = rs;
507 let Inst{20-16} = rt;
508 let Inst{15-6} = code_;
509 let Inst{5-0} = funct;
512 class TEQI_FM<bits<5> funct> : StdArch {
519 let Inst{25-21} = rs;
520 let Inst{20-16} = funct;
521 let Inst{15-0} = imm16;
524 class WAIT_FM : StdArch {
527 let Inst{31-26} = 0x10;
530 let Inst{5-0} = 0x20;
533 class EXTS_FM<bits<6> funct> : StdArch {
541 let Inst{31-26} = 0x1c;
542 let Inst{25-21} = rs;
543 let Inst{20-16} = rt;
544 let Inst{15-11} = lenm1;
545 let Inst{10-6} = pos;
546 let Inst{5-0} = funct;
549 class MTMR_FM<bits<6> funct> : StdArch {
554 let Inst{31-26} = 0x1c;
555 let Inst{25-21} = rs;
557 let Inst{5-0} = funct;
560 class POP_FM<bits<6> funct> : StdArch {
566 let Inst{31-26} = 0x1c;
567 let Inst{25-21} = rs;
569 let Inst{15-11} = rd;
571 let Inst{5-0} = funct;
574 class SEQ_FM<bits<6> funct> : StdArch {
581 let Inst{31-26} = 0x1c;
582 let Inst{25-21} = rs;
583 let Inst{20-16} = rt;
584 let Inst{15-11} = rd;
586 let Inst{5-0} = funct;
589 class SEQI_FM<bits<6> funct> : StdArch {
596 let Inst{31-26} = 0x1c;
597 let Inst{25-21} = rs;
598 let Inst{20-16} = rt;
599 let Inst{15-6} = imm10;
600 let Inst{5-0} = funct;
603 //===----------------------------------------------------------------------===//
604 // System calls format <op|code_|funct>
605 //===----------------------------------------------------------------------===//
607 class SYS_FM<bits<6> funct> : StdArch
611 let Inst{31-26} = 0x0;
612 let Inst{25-6} = code_;
613 let Inst{5-0} = funct;
616 //===----------------------------------------------------------------------===//
617 // Break instruction format <op|code_1|funct>
618 //===----------------------------------------------------------------------===//
620 class BRK_FM<bits<6> funct> : StdArch
625 let Inst{31-26} = 0x0;
626 let Inst{25-16} = code_1;
627 let Inst{15-6} = code_2;
628 let Inst{5-0} = funct;
631 //===----------------------------------------------------------------------===//
632 // Exception return format <Cop0|1|0|funct>
633 //===----------------------------------------------------------------------===//
635 class ER_FM<bits<6> funct> : StdArch
638 let Inst{31-26} = 0x10;
641 let Inst{5-0} = funct;
645 //===----------------------------------------------------------------------===//
646 // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
647 //===----------------------------------------------------------------------===//
649 class EI_FM<bits<1> sc> : StdArch
653 let Inst{31-26} = 0x10;
654 let Inst{25-21} = 0xb;
655 let Inst{20-16} = rt;
656 let Inst{15-11} = 0xc;
662 //===----------------------------------------------------------------------===//
664 // FLOATING POINT INSTRUCTION FORMATS
666 // opcode - operation code.
668 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
669 // fd - dst reg, only used on 3 regs instr.
670 // fmt - double or single precision.
671 // funct - combined with opcode field give us an operation code.
673 //===----------------------------------------------------------------------===//
675 //===----------------------------------------------------------------------===//
676 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
677 //===----------------------------------------------------------------------===//
679 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
680 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
688 let Inst{25-21} = base;
689 let Inst{20-16} = ft;
690 let Inst{15-0} = imm16;
693 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
700 let Inst{31-26} = 0x11;
701 let Inst{25-21} = fmt;
702 let Inst{20-16} = ft;
703 let Inst{15-11} = fs;
705 let Inst{5-0} = funct;
708 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
714 let Inst{31-26} = 0x11;
715 let Inst{25-21} = fmt;
717 let Inst{15-11} = fs;
719 let Inst{5-0} = funct;
722 class MFC1_FM<bits<5> funct> : StdArch {
728 let Inst{31-26} = 0x11;
729 let Inst{25-21} = funct;
730 let Inst{20-16} = rt;
731 let Inst{15-11} = fs;
735 class LW_FM<bits<6> op> : StdArch {
741 let Inst{31-26} = op;
742 let Inst{25-21} = addr{20-16};
743 let Inst{20-16} = rt;
744 let Inst{15-0} = addr{15-0};
747 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
755 let Inst{31-26} = 0x13;
756 let Inst{25-21} = fr;
757 let Inst{20-16} = ft;
758 let Inst{15-11} = fs;
760 let Inst{5-3} = funct;
764 class LWXC1_FM<bits<6> funct> : StdArch {
771 let Inst{31-26} = 0x13;
772 let Inst{25-21} = base;
773 let Inst{20-16} = index;
776 let Inst{5-0} = funct;
779 class SWXC1_FM<bits<6> funct> : StdArch {
786 let Inst{31-26} = 0x13;
787 let Inst{25-21} = base;
788 let Inst{20-16} = index;
789 let Inst{15-11} = fs;
791 let Inst{5-0} = funct;
794 class BC1F_FM<bit nd, bit tf> : StdArch {
800 let Inst{31-26} = 0x11;
801 let Inst{25-21} = 0x8;
802 let Inst{20-18} = fcc;
805 let Inst{15-0} = offset;
808 class CEQS_FM<bits<5> fmt> : StdArch {
815 let Inst{31-26} = 0x11;
816 let Inst{25-21} = fmt;
817 let Inst{20-16} = ft;
818 let Inst{15-11} = fs;
819 let Inst{10-8} = 0; // cc
821 let Inst{3-0} = cond;
824 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
828 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
835 let Inst{31-26} = 0x11;
836 let Inst{25-21} = fmt;
837 let Inst{20-16} = rt;
838 let Inst{15-11} = fs;
840 let Inst{5-0} = funct;
843 class CMov_F_I_FM<bit tf> : StdArch {
851 let Inst{25-21} = rs;
852 let Inst{20-18} = fcc;
855 let Inst{15-11} = rd;
860 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
867 let Inst{31-26} = 0x11;
868 let Inst{25-21} = fmt;
869 let Inst{20-18} = fcc;
872 let Inst{15-11} = fs;
874 let Inst{5-0} = 0x11;
877 class BARRIER_FM<bits<5> op> : StdArch {
880 let Inst{31-26} = 0; // SPECIAL
882 let Inst{20-16} = 0; // rt = 0
883 let Inst{15-11} = 0; // rd = 0
884 let Inst{10-6} = op; // Operation
885 let Inst{5-0} = 0; // SLL
888 class SDBBP_FM : StdArch {
893 let Inst{31-26} = 0b011100; // SPECIAL2
894 let Inst{25-6} = code_;
895 let Inst{5-0} = 0b111111; // SDBBP
898 class JR_HB_FM<bits<6> op> : StdArch{
903 let Inst{31-26} = 0; // SPECIAL
904 let Inst{25-21} = rs;
911 class JALR_HB_FM<bits<6> op> : StdArch {
917 let Inst{31-26} = 0; // SPECIAL
918 let Inst{25-21} = rs;
920 let Inst{15-11} = rd;
926 class COP0_TLB_FM<bits<6> op> : StdArch {
929 let Inst{31-26} = 0x10; // COP0
930 let Inst{25} = 1; // CO
932 let Inst{5-0} = op; // Operation
935 class CACHEOP_FM<bits<6> op> : StdArch {
938 bits<5> base = addr{20-16};
939 bits<16> offset = addr{15-0};
943 let Inst{31-26} = op;
944 let Inst{25-21} = base;
945 let Inst{20-16} = hint;
946 let Inst{15-0} = offset;