1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
57 // Generic Mips Format
58 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
59 InstrItinClass itin, Format f>: Instruction
64 let Namespace = "Mips";
70 // Top 6 bits are the 'opcode' field
71 let Inst{31-26} = Opcode;
73 let OutOperandList = outs;
74 let InOperandList = ins;
76 let AsmString = asmstr;
77 let Pattern = pattern;
81 // Attributes specific to Mips instructions...
83 bits<4> FormBits = Form.Value;
85 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
86 let TSFlags{3-0} = FormBits;
88 let DecoderNamespace = "Mips";
90 field bits<32> SoftFail = 0;
93 // Mips32/64 Instruction Format
94 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
95 InstrItinClass itin, Format f, string opstr = ""> :
96 MipsInst<outs, ins, asmstr, pattern, itin, f> {
97 let Predicates = [HasStdEnc];
98 string BaseOpcode = opstr;
102 // Mips Pseudo Instructions Format
103 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
104 InstrItinClass itin = IIPseudo> :
105 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
106 let isCodeGenOnly = 1;
110 // Mips32/64 Pseudo Instruction Format
111 class PseudoSE<dag outs, dag ins, list<dag> pattern,
112 InstrItinClass itin = IIPseudo>:
113 MipsPseudo<outs, ins, pattern, itin> {
114 let Predicates = [HasStdEnc];
117 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
118 // These are aliases that require C++ handling to convert to the target
119 // instruction, while InstAliases can be handled directly by tblgen.
120 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
125 //===----------------------------------------------------------------------===//
126 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
127 //===----------------------------------------------------------------------===//
129 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
130 list<dag> pattern, InstrItinClass itin>:
131 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
142 let Inst{25-21} = rs;
143 let Inst{20-16} = rt;
144 let Inst{15-11} = rd;
145 let Inst{10-6} = shamt;
146 let Inst{5-0} = funct;
149 //===----------------------------------------------------------------------===//
150 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
151 //===----------------------------------------------------------------------===//
153 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
162 let Inst{25-21} = rs;
163 let Inst{20-16} = rt;
164 let Inst{15-0} = imm16;
167 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
168 list<dag> pattern, InstrItinClass itin>:
169 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
177 let Inst{25-21} = rs;
178 let Inst{20-16} = rt;
179 let Inst{15-0} = imm16;
182 //===----------------------------------------------------------------------===//
183 // Format J instruction class in Mips : <|opcode|address|>
184 //===----------------------------------------------------------------------===//
192 let Inst{31-26} = op;
193 let Inst{25-0} = target;
196 //===----------------------------------------------------------------------===//
197 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
198 //===----------------------------------------------------------------------===//
199 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
207 let Inst{31-26} = op;
208 let Inst{25-21} = mfmt;
209 let Inst{20-16} = rt;
210 let Inst{15-11} = rd;
215 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
222 let Inst{31-26} = op;
223 let Inst{25-21} = rs;
224 let Inst{20-16} = rt;
225 let Inst{15-11} = rd;
227 let Inst{5-0} = funct;
230 class ADDI_FM<bits<6> op> : StdArch {
237 let Inst{31-26} = op;
238 let Inst{25-21} = rs;
239 let Inst{20-16} = rt;
240 let Inst{15-0} = imm16;
243 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
252 let Inst{21} = rotate;
253 let Inst{20-16} = rt;
254 let Inst{15-11} = rd;
255 let Inst{10-6} = shamt;
256 let Inst{5-0} = funct;
259 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
267 let Inst{25-21} = rs;
268 let Inst{20-16} = rt;
269 let Inst{15-11} = rd;
271 let Inst{6} = rotate;
272 let Inst{5-0} = funct;
275 class BEQ_FM<bits<6> op> {
282 let Inst{31-26} = op;
283 let Inst{25-21} = rs;
284 let Inst{20-16} = rt;
285 let Inst{15-0} = offset;
288 class BGEZ_FM<bits<6> op, bits<5> funct> {
294 let Inst{31-26} = op;
295 let Inst{25-21} = rs;
296 let Inst{20-16} = funct;
297 let Inst{15-0} = offset;
308 let Inst{15-0} = offset;
311 class SLTI_FM<bits<6> op> : StdArch {
318 let Inst{31-26} = op;
319 let Inst{25-21} = rs;
320 let Inst{20-16} = rt;
321 let Inst{15-0} = imm16;
324 class MFLO_FM<bits<6> funct> {
331 let Inst{15-11} = rd;
333 let Inst{5-0} = funct;
336 class MTLO_FM<bits<6> funct> {
342 let Inst{25-21} = rs;
344 let Inst{5-0} = funct;
347 class SEB_FM<bits<5> funct, bits<6> funct2> {
353 let Inst{31-26} = 0x1f;
355 let Inst{20-16} = rt;
356 let Inst{15-11} = rd;
357 let Inst{10-6} = funct;
358 let Inst{5-0} = funct2;
361 class CLO_FM<bits<6> funct> {
368 let Inst{31-26} = 0x1c;
369 let Inst{25-21} = rs;
370 let Inst{20-16} = rt;
371 let Inst{15-11} = rd;
373 let Inst{5-0} = funct;
383 let Inst{31-26} = 0xf;
385 let Inst{20-16} = rt;
386 let Inst{15-0} = imm16;
396 let Inst{25-21} = rs;
398 let Inst{15-11} = rd;
403 class BGEZAL_FM<bits<5> funct> {
410 let Inst{25-21} = rs;
411 let Inst{20-16} = funct;
412 let Inst{15-0} = offset;
421 let Inst{10-6} = stype;
425 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
431 let Inst{31-26} = op;
432 let Inst{25-21} = rs;
433 let Inst{20-16} = rt;
435 let Inst{5-0} = funct;
438 class EXT_FM<bits<6> funct> {
446 let Inst{31-26} = 0x1f;
447 let Inst{25-21} = rs;
448 let Inst{20-16} = rt;
449 let Inst{15-11} = size;
450 let Inst{10-6} = pos;
451 let Inst{5-0} = funct;
460 let Inst{31-26} = 0x1f;
462 let Inst{20-16} = rt;
463 let Inst{15-11} = rd;
465 let Inst{5-0} = 0x3b;
468 class TEQ_FM<bits<6> funct> {
476 let Inst{25-21} = rs;
477 let Inst{20-16} = rt;
478 let Inst{15-6} = code_;
479 let Inst{5-0} = funct;
482 //===----------------------------------------------------------------------===//
483 // System calls format <op|code_|funct>
484 //===----------------------------------------------------------------------===//
486 class SYS_FM<bits<6> funct>
490 let Inst{31-26} = 0x0;
491 let Inst{25-6} = code_;
492 let Inst{5-0} = funct;
495 //===----------------------------------------------------------------------===//
496 // Break instruction format <op|code_1|funct>
497 //===----------------------------------------------------------------------===//
499 class BRK_FM<bits<6> funct>
504 let Inst{31-26} = 0x0;
505 let Inst{25-16} = code_1;
506 let Inst{15-6} = code_2;
507 let Inst{5-0} = funct;
510 //===----------------------------------------------------------------------===//
511 // Exception return format <Cop0|1|0|funct>
512 //===----------------------------------------------------------------------===//
514 class ER_FM<bits<6> funct>
517 let Inst{31-26} = 0x10;
520 let Inst{5-0} = funct;
523 //===----------------------------------------------------------------------===//
525 // FLOATING POINT INSTRUCTION FORMATS
527 // opcode - operation code.
529 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
530 // fd - dst reg, only used on 3 regs instr.
531 // fmt - double or single precision.
532 // funct - combined with opcode field give us an operation code.
534 //===----------------------------------------------------------------------===//
536 //===----------------------------------------------------------------------===//
537 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
538 //===----------------------------------------------------------------------===//
540 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
541 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
549 let Inst{25-21} = base;
550 let Inst{20-16} = ft;
551 let Inst{15-0} = imm16;
554 class ADDS_FM<bits<6> funct, bits<5> fmt> {
561 let Inst{31-26} = 0x11;
562 let Inst{25-21} = fmt;
563 let Inst{20-16} = ft;
564 let Inst{15-11} = fs;
566 let Inst{5-0} = funct;
569 class ABSS_FM<bits<6> funct, bits<5> fmt> {
575 let Inst{31-26} = 0x11;
576 let Inst{25-21} = fmt;
578 let Inst{15-11} = fs;
580 let Inst{5-0} = funct;
583 class MFC1_FM<bits<5> funct> {
589 let Inst{31-26} = 0x11;
590 let Inst{25-21} = funct;
591 let Inst{20-16} = rt;
592 let Inst{15-11} = fs;
596 class LW_FM<bits<6> op> : StdArch {
602 let Inst{31-26} = op;
603 let Inst{25-21} = addr{20-16};
604 let Inst{20-16} = rt;
605 let Inst{15-0} = addr{15-0};
608 class MADDS_FM<bits<3> funct, bits<3> fmt> {
616 let Inst{31-26} = 0x13;
617 let Inst{25-21} = fr;
618 let Inst{20-16} = ft;
619 let Inst{15-11} = fs;
621 let Inst{5-3} = funct;
625 class LWXC1_FM<bits<6> funct> {
632 let Inst{31-26} = 0x13;
633 let Inst{25-21} = base;
634 let Inst{20-16} = index;
637 let Inst{5-0} = funct;
640 class SWXC1_FM<bits<6> funct> {
647 let Inst{31-26} = 0x13;
648 let Inst{25-21} = base;
649 let Inst{20-16} = index;
650 let Inst{15-11} = fs;
652 let Inst{5-0} = funct;
655 class BC1F_FM<bit nd, bit tf> {
661 let Inst{31-26} = 0x11;
662 let Inst{25-21} = 0x8;
663 let Inst{20-18} = fcc;
666 let Inst{15-0} = offset;
669 class CEQS_FM<bits<5> fmt> {
676 let Inst{31-26} = 0x11;
677 let Inst{25-21} = fmt;
678 let Inst{20-16} = ft;
679 let Inst{15-11} = fs;
680 let Inst{10-8} = 0; // cc
682 let Inst{3-0} = cond;
685 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
689 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
696 let Inst{31-26} = 0x11;
697 let Inst{25-21} = fmt;
698 let Inst{20-16} = rt;
699 let Inst{15-11} = fs;
701 let Inst{5-0} = funct;
704 class CMov_F_I_FM<bit tf> {
712 let Inst{25-21} = rs;
713 let Inst{20-18} = fcc;
716 let Inst{15-11} = rd;
721 class CMov_F_F_FM<bits<5> fmt, bit tf> {
728 let Inst{31-26} = 0x11;
729 let Inst{25-21} = fmt;
730 let Inst{20-18} = fcc;
733 let Inst{15-11} = fs;
735 let Inst{5-0} = 0x11;