1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
39 // Generic Mips Format
40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41 InstrItinClass itin, Format f>: Instruction
46 let Namespace = "Mips";
52 // Top 6 bits are the 'opcode' field
53 let Inst{31-26} = Opcode;
55 let OutOperandList = outs;
56 let InOperandList = ins;
58 let AsmString = asmstr;
59 let Pattern = pattern;
63 // Attributes specific to Mips instructions...
65 bits<4> FormBits = Form.Value;
67 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68 let TSFlags{3-0} = FormBits;
70 let DecoderNamespace = "Mips";
72 field bits<32> SoftFail = 0;
74 let Predicates = [HasStandardEncoding];
78 // Mips Pseudo Instructions Format
79 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
80 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
81 let isCodeGenOnly = 1;
85 //===----------------------------------------------------------------------===//
86 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
87 //===----------------------------------------------------------------------===//
89 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
90 list<dag> pattern, InstrItinClass itin>:
91 MipsInst<outs, ins, asmstr, pattern, itin, FrmR>
102 let Inst{25-21} = rs;
103 let Inst{20-16} = rt;
104 let Inst{15-11} = rd;
105 let Inst{10-6} = shamt;
106 let Inst{5-0} = funct;
109 //===----------------------------------------------------------------------===//
110 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
111 //===----------------------------------------------------------------------===//
113 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
114 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmI>
122 let Inst{25-21} = rs;
123 let Inst{20-16} = rt;
124 let Inst{15-0} = imm16;
127 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
128 list<dag> pattern, InstrItinClass itin>:
129 MipsInst<outs, ins, asmstr, pattern, itin, FrmI>
137 let Inst{25-21} = rs;
138 let Inst{20-16} = rt;
139 let Inst{15-0} = imm16;
142 //===----------------------------------------------------------------------===//
143 // Format J instruction class in Mips : <|opcode|address|>
144 //===----------------------------------------------------------------------===//
146 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
147 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmJ>
153 let Inst{25-0} = addr;
156 //===----------------------------------------------------------------------===//
158 // FLOATING POINT INSTRUCTION FORMATS
160 // opcode - operation code.
162 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
163 // fd - dst reg, only used on 3 regs instr.
164 // fmt - double or single precision.
165 // funct - combined with opcode field give us an operation code.
167 //===----------------------------------------------------------------------===//
169 //===----------------------------------------------------------------------===//
170 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
171 //===----------------------------------------------------------------------===//
173 class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
174 string asmstr, list<dag> pattern> :
175 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFR>
187 let Inst{25-21} = fmt;
188 let Inst{20-16} = ft;
189 let Inst{15-11} = fs;
191 let Inst{5-0} = funct;
194 //===----------------------------------------------------------------------===//
195 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
196 //===----------------------------------------------------------------------===//
198 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
199 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
207 let Inst{25-21} = base;
208 let Inst{20-16} = ft;
209 let Inst{15-0} = imm16;
212 //===----------------------------------------------------------------------===//
213 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
214 //===----------------------------------------------------------------------===//
216 class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
217 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
227 let Inst{25-21} = fmt;
228 let Inst{20-16} = ft;
229 let Inst{15-11} = fs;
231 let Inst{5-4} = 0b11;
236 class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
238 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
248 let Inst{25-21} = rs;
249 let Inst{20-18} = cc;
252 let Inst{15-11} = rd;
257 class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
259 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
271 let Inst{25-21} = fmt;
272 let Inst{20-18} = cc;
275 let Inst{15-11} = fs;
280 // FP unary instructions without patterns.
281 class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
282 RegisterClass DstRC, RegisterClass SrcRC> :
283 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
284 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
288 // FP unary instructions with patterns.
289 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
290 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
291 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
292 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
293 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
297 class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
298 string fmtstr, RegisterClass RC, SDNode OpNode> :
299 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
300 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
301 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
303 // Floating point madd/msub/nmadd/nmsub.
304 class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
306 : MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> {
313 let Inst{25-21} = fr;
314 let Inst{20-16} = ft;
315 let Inst{15-11} = fs;
317 let Inst{5-3} = funct;
321 // FP indexed load/store instructions.
322 class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr,
324 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
333 let Inst{25-21} = base;
334 let Inst{20-16} = index;
335 let Inst{15-11} = fs;
337 let Inst{5-0} = funct;