1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
39 // Generic Mips Format
40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41 InstrItinClass itin, Format f>: Instruction
46 let Namespace = "Mips";
52 // Top 6 bits are the 'opcode' field
53 let Inst{31-26} = Opcode;
55 let OutOperandList = outs;
56 let InOperandList = ins;
58 let AsmString = asmstr;
59 let Pattern = pattern;
63 // Attributes specific to Mips instructions...
65 bits<4> FormBits = Form.Value;
67 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68 let TSFlags{3-0} = FormBits;
70 let DecoderNamespace = "Mips";
72 field bits<32> SoftFail = 0;
75 // Mips32/64 Instruction Format
76 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77 InstrItinClass itin, Format f>:
78 MipsInst<outs, ins, asmstr, pattern, itin, f> {
79 let Predicates = [HasStdEnc];
82 // Mips Pseudo Instructions Format
83 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
84 InstrItinClass itin = IIPseudo> :
85 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
86 let isCodeGenOnly = 1;
90 // Mips32/64 Pseudo Instruction Format
91 class PseudoSE<dag outs, dag ins, list<dag> pattern,
92 InstrItinClass itin = IIPseudo>:
93 MipsPseudo<outs, ins, pattern, itin> {
94 let Predicates = [HasStdEnc];
97 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
98 // These are aliases that require C++ handling to convert to the target
99 // instruction, while InstAliases can be handled directly by tblgen.
100 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
101 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
105 //===----------------------------------------------------------------------===//
106 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
107 //===----------------------------------------------------------------------===//
109 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
110 list<dag> pattern, InstrItinClass itin>:
111 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
122 let Inst{25-21} = rs;
123 let Inst{20-16} = rt;
124 let Inst{15-11} = rd;
125 let Inst{10-6} = shamt;
126 let Inst{5-0} = funct;
129 //===----------------------------------------------------------------------===//
130 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
131 //===----------------------------------------------------------------------===//
133 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
134 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
142 let Inst{25-21} = rs;
143 let Inst{20-16} = rt;
144 let Inst{15-0} = imm16;
147 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
148 list<dag> pattern, InstrItinClass itin>:
149 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
157 let Inst{25-21} = rs;
158 let Inst{20-16} = rt;
159 let Inst{15-0} = imm16;
162 //===----------------------------------------------------------------------===//
163 // Format J instruction class in Mips : <|opcode|address|>
164 //===----------------------------------------------------------------------===//
166 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
167 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
173 let Inst{25-0} = addr;
176 //===----------------------------------------------------------------------===//
177 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
178 //===----------------------------------------------------------------------===//
179 class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
180 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
190 let Inst{25-21} = mfmt;
191 let Inst{20-16} = rt;
192 let Inst{15-11} = rd;
197 class ADD_FM<bits<6> op, bits<6> funct> {
204 let Inst{31-26} = op;
205 let Inst{25-21} = rs;
206 let Inst{20-16} = rt;
207 let Inst{15-11} = rd;
209 let Inst{5-0} = funct;
212 class ADDI_FM<bits<6> op> {
219 let Inst{31-26} = op;
220 let Inst{25-21} = rs;
221 let Inst{20-16} = rt;
222 let Inst{15-0} = imm16;
225 class SRA_FM<bits<6> funct, bit rotate> {
234 let Inst{21} = rotate;
235 let Inst{20-16} = rt;
236 let Inst{15-11} = rd;
237 let Inst{10-6} = shamt;
238 let Inst{5-0} = funct;
241 class SRLV_FM<bits<6> funct, bit rotate> {
249 let Inst{25-21} = rs;
250 let Inst{20-16} = rt;
251 let Inst{15-11} = rd;
253 let Inst{6} = rotate;
254 let Inst{5-0} = funct;
257 class BEQ_FM<bits<6> op> {
264 let Inst{31-26} = op;
265 let Inst{25-21} = rs;
266 let Inst{20-16} = rt;
267 let Inst{15-0} = offset;
270 class BGEZ_FM<bits<6> op, bits<5> funct> {
276 let Inst{31-26} = op;
277 let Inst{25-21} = rs;
278 let Inst{20-16} = funct;
279 let Inst{15-0} = offset;
290 let Inst{15-0} = offset;
293 class SLTI_FM<bits<6> op> {
300 let Inst{31-26} = op;
301 let Inst{25-21} = rs;
302 let Inst{20-16} = rt;
303 let Inst{15-0} = imm16;
306 //===----------------------------------------------------------------------===//
308 // FLOATING POINT INSTRUCTION FORMATS
310 // opcode - operation code.
312 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
313 // fd - dst reg, only used on 3 regs instr.
314 // fmt - double or single precision.
315 // funct - combined with opcode field give us an operation code.
317 //===----------------------------------------------------------------------===//
319 //===----------------------------------------------------------------------===//
320 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
321 //===----------------------------------------------------------------------===//
323 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
324 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
332 let Inst{25-21} = base;
333 let Inst{20-16} = ft;
334 let Inst{15-0} = imm16;
337 class ADDS_FM<bits<6> funct, bits<5> fmt> {
344 let Inst{31-26} = 0x11;
345 let Inst{25-21} = fmt;
346 let Inst{20-16} = ft;
347 let Inst{15-11} = fs;
349 let Inst{5-0} = funct;
352 class ABSS_FM<bits<6> funct, bits<5> fmt> {
358 let Inst{31-26} = 0x11;
359 let Inst{25-21} = fmt;
361 let Inst{15-11} = fs;
363 let Inst{5-0} = funct;
366 class MFC1_FM<bits<5> funct> {
372 let Inst{31-26} = 0x11;
373 let Inst{25-21} = funct;
374 let Inst{20-16} = rt;
375 let Inst{15-11} = fs;
379 class LW_FM<bits<6> op> {
385 let Inst{31-26} = op;
386 let Inst{25-21} = addr{20-16};
387 let Inst{20-16} = rt;
388 let Inst{15-0} = addr{15-0};
391 class MADDS_FM<bits<3> funct, bits<3> fmt> {
399 let Inst{31-26} = 0x13;
400 let Inst{25-21} = fr;
401 let Inst{20-16} = ft;
402 let Inst{15-11} = fs;
404 let Inst{5-3} = funct;
408 class LWXC1_FM<bits<6> funct> {
415 let Inst{31-26} = 0x13;
416 let Inst{25-21} = base;
417 let Inst{20-16} = index;
420 let Inst{5-0} = funct;
423 class SWXC1_FM<bits<6> funct> {
430 let Inst{31-26} = 0x13;
431 let Inst{25-21} = base;
432 let Inst{20-16} = index;
433 let Inst{15-11} = fs;
435 let Inst{5-0} = funct;
438 class BC1F_FM<bit nd, bit tf> {
443 let Inst{31-26} = 0x11;
444 let Inst{25-21} = 0x8;
445 let Inst{20-18} = 0; // cc
448 let Inst{15-0} = offset;
451 class CEQS_FM<bits<5> fmt> {
458 let Inst{31-26} = 0x11;
459 let Inst{25-21} = fmt;
460 let Inst{20-16} = ft;
461 let Inst{15-11} = fs;
462 let Inst{10-8} = 0; // cc
464 let Inst{3-0} = cond;
467 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
474 let Inst{31-26} = 0x11;
475 let Inst{25-21} = fmt;
476 let Inst{20-16} = rt;
477 let Inst{15-11} = fs;
479 let Inst{5-0} = funct;
482 class CMov_F_I_FM<bit tf> {
489 let Inst{25-21} = rs;
490 let Inst{20-18} = 0; // cc
493 let Inst{15-11} = rd;
498 class CMov_F_F_FM<bits<5> fmt, bit tf> {
504 let Inst{31-26} = 0x11;
505 let Inst{25-21} = fmt;
506 let Inst{20-18} = 0; // cc
509 let Inst{15-11} = fs;
511 let Inst{5-0} = 0x11;