1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
57 // Generic Mips Format
58 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
59 InstrItinClass itin, Format f>: Instruction
64 let Namespace = "Mips";
70 // Top 6 bits are the 'opcode' field
71 let Inst{31-26} = Opcode;
73 let OutOperandList = outs;
74 let InOperandList = ins;
76 let AsmString = asmstr;
77 let Pattern = pattern;
81 // Attributes specific to Mips instructions...
83 bits<4> FormBits = Form.Value;
85 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
86 let TSFlags{3-0} = FormBits;
88 let DecoderNamespace = "Mips";
90 field bits<32> SoftFail = 0;
93 // Mips32/64 Instruction Format
94 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
95 InstrItinClass itin, Format f, string opstr = ""> :
96 MipsInst<outs, ins, asmstr, pattern, itin, f> {
97 let Predicates = [HasStdEnc];
98 string BaseOpcode = opstr;
102 // Mips Pseudo Instructions Format
103 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
104 InstrItinClass itin = IIPseudo> :
105 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
106 let isCodeGenOnly = 1;
110 // Mips32/64 Pseudo Instruction Format
111 class PseudoSE<dag outs, dag ins, list<dag> pattern,
112 InstrItinClass itin = IIPseudo>:
113 MipsPseudo<outs, ins, pattern, itin> {
114 let Predicates = [HasStdEnc];
117 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
118 // These are aliases that require C++ handling to convert to the target
119 // instruction, while InstAliases can be handled directly by tblgen.
120 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
125 //===----------------------------------------------------------------------===//
126 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
127 //===----------------------------------------------------------------------===//
129 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
130 list<dag> pattern, InstrItinClass itin>:
131 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
142 let Inst{25-21} = rs;
143 let Inst{20-16} = rt;
144 let Inst{15-11} = rd;
145 let Inst{10-6} = shamt;
146 let Inst{5-0} = funct;
149 //===----------------------------------------------------------------------===//
150 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
151 //===----------------------------------------------------------------------===//
153 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
162 let Inst{25-21} = rs;
163 let Inst{20-16} = rt;
164 let Inst{15-0} = imm16;
167 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
168 list<dag> pattern, InstrItinClass itin>:
169 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
177 let Inst{25-21} = rs;
178 let Inst{20-16} = rt;
179 let Inst{15-0} = imm16;
182 //===----------------------------------------------------------------------===//
183 // Format J instruction class in Mips : <|opcode|address|>
184 //===----------------------------------------------------------------------===//
186 class FJ<bits<6> op> : StdArch
192 let Inst{31-26} = op;
193 let Inst{25-0} = target;
196 //===----------------------------------------------------------------------===//
197 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
198 //===----------------------------------------------------------------------===//
199 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
207 let Inst{31-26} = op;
208 let Inst{25-21} = mfmt;
209 let Inst{20-16} = rt;
210 let Inst{15-11} = rd;
215 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
222 let Inst{31-26} = op;
223 let Inst{25-21} = rs;
224 let Inst{20-16} = rt;
225 let Inst{15-11} = rd;
227 let Inst{5-0} = funct;
230 class ADDI_FM<bits<6> op> : StdArch {
237 let Inst{31-26} = op;
238 let Inst{25-21} = rs;
239 let Inst{20-16} = rt;
240 let Inst{15-0} = imm16;
243 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
252 let Inst{21} = rotate;
253 let Inst{20-16} = rt;
254 let Inst{15-11} = rd;
255 let Inst{10-6} = shamt;
256 let Inst{5-0} = funct;
259 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
267 let Inst{25-21} = rs;
268 let Inst{20-16} = rt;
269 let Inst{15-11} = rd;
271 let Inst{6} = rotate;
272 let Inst{5-0} = funct;
275 class BEQ_FM<bits<6> op> : StdArch {
282 let Inst{31-26} = op;
283 let Inst{25-21} = rs;
284 let Inst{20-16} = rt;
285 let Inst{15-0} = offset;
288 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
294 let Inst{31-26} = op;
295 let Inst{25-21} = rs;
296 let Inst{20-16} = funct;
297 let Inst{15-0} = offset;
300 class SLTI_FM<bits<6> op> : StdArch {
307 let Inst{31-26} = op;
308 let Inst{25-21} = rs;
309 let Inst{20-16} = rt;
310 let Inst{15-0} = imm16;
313 class MFLO_FM<bits<6> funct> : StdArch {
320 let Inst{15-11} = rd;
322 let Inst{5-0} = funct;
325 class MTLO_FM<bits<6> funct> : StdArch {
331 let Inst{25-21} = rs;
333 let Inst{5-0} = funct;
336 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
342 let Inst{31-26} = 0x1f;
344 let Inst{20-16} = rt;
345 let Inst{15-11} = rd;
346 let Inst{10-6} = funct;
347 let Inst{5-0} = funct2;
350 class CLO_FM<bits<6> funct> : StdArch {
357 let Inst{31-26} = 0x1c;
358 let Inst{25-21} = rs;
359 let Inst{20-16} = rt;
360 let Inst{15-11} = rd;
362 let Inst{5-0} = funct;
366 class LUI_FM : StdArch {
372 let Inst{31-26} = 0xf;
374 let Inst{20-16} = rt;
375 let Inst{15-0} = imm16;
385 let Inst{25-21} = rs;
387 let Inst{15-11} = rd;
392 class BGEZAL_FM<bits<5> funct> : StdArch {
399 let Inst{25-21} = rs;
400 let Inst{20-16} = funct;
401 let Inst{15-0} = offset;
404 class SYNC_FM : StdArch {
410 let Inst{10-6} = stype;
414 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
420 let Inst{31-26} = op;
421 let Inst{25-21} = rs;
422 let Inst{20-16} = rt;
424 let Inst{5-0} = funct;
427 class EXT_FM<bits<6> funct> : StdArch {
435 let Inst{31-26} = 0x1f;
436 let Inst{25-21} = rs;
437 let Inst{20-16} = rt;
438 let Inst{15-11} = size;
439 let Inst{10-6} = pos;
440 let Inst{5-0} = funct;
449 let Inst{31-26} = 0x1f;
451 let Inst{20-16} = rt;
452 let Inst{15-11} = rd;
454 let Inst{5-0} = 0x3b;
457 class TEQ_FM<bits<6> funct> : StdArch {
465 let Inst{25-21} = rs;
466 let Inst{20-16} = rt;
467 let Inst{15-6} = code_;
468 let Inst{5-0} = funct;
471 class TEQI_FM<bits<5> funct> : StdArch {
478 let Inst{25-21} = rs;
479 let Inst{20-16} = funct;
480 let Inst{15-0} = imm16;
483 class WAIT_FM : StdArch {
486 let Inst{31-26} = 0x10;
489 let Inst{5-0} = 0x20;
492 class MTMR_FM<bits<6> funct> : StdArch {
497 let Inst{31-26} = 0x1c;
498 let Inst{25-21} = rs;
500 let Inst{5-0} = funct;
503 class POP_FM<bits<6> funct> : StdArch {
509 let Inst{31-26} = 0x1c;
510 let Inst{25-21} = rs;
512 let Inst{15-11} = rd;
514 let Inst{5-0} = funct;
517 class SEQ_FM<bits<6> funct> : StdArch {
524 let Inst{31-26} = 0x1c;
525 let Inst{25-21} = rs;
526 let Inst{20-16} = rt;
527 let Inst{15-11} = rd;
529 let Inst{5-0} = funct;
532 //===----------------------------------------------------------------------===//
533 // System calls format <op|code_|funct>
534 //===----------------------------------------------------------------------===//
536 class SYS_FM<bits<6> funct> : StdArch
540 let Inst{31-26} = 0x0;
541 let Inst{25-6} = code_;
542 let Inst{5-0} = funct;
545 //===----------------------------------------------------------------------===//
546 // Break instruction format <op|code_1|funct>
547 //===----------------------------------------------------------------------===//
549 class BRK_FM<bits<6> funct> : StdArch
554 let Inst{31-26} = 0x0;
555 let Inst{25-16} = code_1;
556 let Inst{15-6} = code_2;
557 let Inst{5-0} = funct;
560 //===----------------------------------------------------------------------===//
561 // Exception return format <Cop0|1|0|funct>
562 //===----------------------------------------------------------------------===//
564 class ER_FM<bits<6> funct> : StdArch
567 let Inst{31-26} = 0x10;
570 let Inst{5-0} = funct;
574 //===----------------------------------------------------------------------===//
575 // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
576 //===----------------------------------------------------------------------===//
578 class EI_FM<bits<1> sc> : StdArch
582 let Inst{31-26} = 0x10;
583 let Inst{25-21} = 0xb;
584 let Inst{20-16} = rt;
585 let Inst{15-11} = 0xc;
591 //===----------------------------------------------------------------------===//
593 // FLOATING POINT INSTRUCTION FORMATS
595 // opcode - operation code.
597 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
598 // fd - dst reg, only used on 3 regs instr.
599 // fmt - double or single precision.
600 // funct - combined with opcode field give us an operation code.
602 //===----------------------------------------------------------------------===//
604 //===----------------------------------------------------------------------===//
605 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
606 //===----------------------------------------------------------------------===//
608 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
609 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
617 let Inst{25-21} = base;
618 let Inst{20-16} = ft;
619 let Inst{15-0} = imm16;
622 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
629 let Inst{31-26} = 0x11;
630 let Inst{25-21} = fmt;
631 let Inst{20-16} = ft;
632 let Inst{15-11} = fs;
634 let Inst{5-0} = funct;
637 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
643 let Inst{31-26} = 0x11;
644 let Inst{25-21} = fmt;
646 let Inst{15-11} = fs;
648 let Inst{5-0} = funct;
651 class MFC1_FM<bits<5> funct> : StdArch {
657 let Inst{31-26} = 0x11;
658 let Inst{25-21} = funct;
659 let Inst{20-16} = rt;
660 let Inst{15-11} = fs;
664 class LW_FM<bits<6> op> : StdArch {
670 let Inst{31-26} = op;
671 let Inst{25-21} = addr{20-16};
672 let Inst{20-16} = rt;
673 let Inst{15-0} = addr{15-0};
676 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
684 let Inst{31-26} = 0x13;
685 let Inst{25-21} = fr;
686 let Inst{20-16} = ft;
687 let Inst{15-11} = fs;
689 let Inst{5-3} = funct;
693 class LWXC1_FM<bits<6> funct> : StdArch {
700 let Inst{31-26} = 0x13;
701 let Inst{25-21} = base;
702 let Inst{20-16} = index;
705 let Inst{5-0} = funct;
708 class SWXC1_FM<bits<6> funct> : StdArch {
715 let Inst{31-26} = 0x13;
716 let Inst{25-21} = base;
717 let Inst{20-16} = index;
718 let Inst{15-11} = fs;
720 let Inst{5-0} = funct;
723 class BC1F_FM<bit nd, bit tf> : StdArch {
729 let Inst{31-26} = 0x11;
730 let Inst{25-21} = 0x8;
731 let Inst{20-18} = fcc;
734 let Inst{15-0} = offset;
737 class CEQS_FM<bits<5> fmt> : StdArch {
744 let Inst{31-26} = 0x11;
745 let Inst{25-21} = fmt;
746 let Inst{20-16} = ft;
747 let Inst{15-11} = fs;
748 let Inst{10-8} = 0; // cc
750 let Inst{3-0} = cond;
753 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
757 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
764 let Inst{31-26} = 0x11;
765 let Inst{25-21} = fmt;
766 let Inst{20-16} = rt;
767 let Inst{15-11} = fs;
769 let Inst{5-0} = funct;
772 class CMov_F_I_FM<bit tf> : StdArch {
780 let Inst{25-21} = rs;
781 let Inst{20-18} = fcc;
784 let Inst{15-11} = rd;
789 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
796 let Inst{31-26} = 0x11;
797 let Inst{25-21} = fmt;
798 let Inst{20-18} = fcc;
801 let Inst{15-11} = fs;
803 let Inst{5-0} = 0x11;