1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
39 // Generic Mips Format
40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41 InstrItinClass itin, Format f>: Instruction
46 let Namespace = "Mips";
52 // Top 6 bits are the 'opcode' field
53 let Inst{31-26} = Opcode;
55 let OutOperandList = outs;
56 let InOperandList = ins;
58 let AsmString = asmstr;
59 let Pattern = pattern;
63 // Attributes specific to Mips instructions...
65 bits<4> FormBits = Form.Value;
67 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68 let TSFlags{3-0} = FormBits;
70 let DecoderNamespace = "Mips";
72 field bits<32> SoftFail = 0;
75 // Mips Pseudo Instructions Format
76 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
77 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
78 let isCodeGenOnly = 1;
82 //===----------------------------------------------------------------------===//
83 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
84 //===----------------------------------------------------------------------===//
86 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
87 list<dag> pattern, InstrItinClass itin>:
88 MipsInst<outs, ins, asmstr, pattern, itin, FrmR>
100 let Inst{20-16} = rt;
101 let Inst{15-11} = rd;
102 let Inst{10-6} = shamt;
103 let Inst{5-0} = funct;
106 //===----------------------------------------------------------------------===//
107 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
108 //===----------------------------------------------------------------------===//
110 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
111 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmI>
119 let Inst{25-21} = rs;
120 let Inst{20-16} = rt;
121 let Inst{15-0} = imm16;
124 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
125 list<dag> pattern, InstrItinClass itin>:
126 MipsInst<outs, ins, asmstr, pattern, itin, FrmI>
134 let Inst{25-21} = rs;
135 let Inst{20-16} = rt;
136 let Inst{15-0} = imm16;
139 //===----------------------------------------------------------------------===//
140 // Format J instruction class in Mips : <|opcode|address|>
141 //===----------------------------------------------------------------------===//
143 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
144 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmJ>
150 let Inst{25-0} = addr;
153 //===----------------------------------------------------------------------===//
155 // FLOATING POINT INSTRUCTION FORMATS
157 // opcode - operation code.
159 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
160 // fd - dst reg, only used on 3 regs instr.
161 // fmt - double or single precision.
162 // funct - combined with opcode field give us an operation code.
164 //===----------------------------------------------------------------------===//
166 //===----------------------------------------------------------------------===//
167 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
168 //===----------------------------------------------------------------------===//
170 class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
171 string asmstr, list<dag> pattern> :
172 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFR>
184 let Inst{25-21} = fmt;
185 let Inst{20-16} = ft;
186 let Inst{15-11} = fs;
188 let Inst{5-0} = funct;
191 //===----------------------------------------------------------------------===//
192 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
193 //===----------------------------------------------------------------------===//
195 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
196 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
204 let Inst{25-21} = base;
205 let Inst{20-16} = ft;
206 let Inst{15-0} = imm16;
209 //===----------------------------------------------------------------------===//
210 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
211 //===----------------------------------------------------------------------===//
213 class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
214 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
224 let Inst{25-21} = fmt;
225 let Inst{20-16} = ft;
226 let Inst{15-11} = fs;
228 let Inst{5-4} = 0b11;
233 class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
235 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
245 let Inst{25-21} = rs;
246 let Inst{20-18} = cc;
249 let Inst{15-11} = rd;
254 class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
256 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
268 let Inst{25-21} = fmt;
269 let Inst{20-18} = cc;
272 let Inst{15-11} = fs;
277 // FP unary instructions without patterns.
278 class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
279 RegisterClass DstRC, RegisterClass SrcRC> :
280 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
281 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
285 // FP unary instructions with patterns.
286 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
287 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
288 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
289 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
290 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
294 class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
295 string fmtstr, RegisterClass RC, SDNode OpNode> :
296 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
297 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
298 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
300 // Floating point madd/msub/nmadd/nmsub.
301 class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
303 : MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther> {
310 let Inst{25-21} = fr;
311 let Inst{20-16} = ft;
312 let Inst{15-11} = fs;
314 let Inst{5-3} = funct;
318 // FP indexed load/store instructions.
319 class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr,
321 MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
330 let Inst{25-21} = base;
331 let Inst{20-16} = index;
332 let Inst{15-11} = fs;
334 let Inst{5-0} = funct;