1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
57 // Generic Mips Format
58 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
59 InstrItinClass itin, Format f>: Instruction
64 let Namespace = "Mips";
70 // Top 6 bits are the 'opcode' field
71 let Inst{31-26} = Opcode;
73 let OutOperandList = outs;
74 let InOperandList = ins;
76 let AsmString = asmstr;
77 let Pattern = pattern;
81 // Attributes specific to Mips instructions...
83 bits<4> FormBits = Form.Value;
85 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
86 let TSFlags{3-0} = FormBits;
88 let DecoderNamespace = "Mips";
90 field bits<32> SoftFail = 0;
93 // Mips32/64 Instruction Format
94 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
95 InstrItinClass itin, Format f, string opstr = ""> :
96 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
97 let EncodingPredicates = [HasStdEnc];
98 string BaseOpcode = opstr;
102 // Mips Pseudo Instructions Format
103 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
104 InstrItinClass itin = IIPseudo> :
105 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
106 let isCodeGenOnly = 1;
110 // Mips32/64 Pseudo Instruction Format
111 class PseudoSE<dag outs, dag ins, list<dag> pattern,
112 InstrItinClass itin = IIPseudo> :
113 MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
114 let EncodingPredicates = [HasStdEnc];
117 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
118 // These are aliases that require C++ handling to convert to the target
119 // instruction, while InstAliases can be handled directly by tblgen.
120 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
125 //===----------------------------------------------------------------------===//
126 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
127 //===----------------------------------------------------------------------===//
129 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
130 list<dag> pattern, InstrItinClass itin>:
131 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
142 let Inst{25-21} = rs;
143 let Inst{20-16} = rt;
144 let Inst{15-11} = rd;
145 let Inst{10-6} = shamt;
146 let Inst{5-0} = funct;
149 //===----------------------------------------------------------------------===//
150 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
151 //===----------------------------------------------------------------------===//
153 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
162 let Inst{25-21} = rs;
163 let Inst{20-16} = rt;
164 let Inst{15-0} = imm16;
167 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
168 list<dag> pattern, InstrItinClass itin>:
169 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
177 let Inst{25-21} = rs;
178 let Inst{20-16} = rt;
179 let Inst{15-0} = imm16;
182 //===----------------------------------------------------------------------===//
183 // Format J instruction class in Mips : <|opcode|address|>
184 //===----------------------------------------------------------------------===//
186 class FJ<bits<6> op> : StdArch
192 let Inst{31-26} = op;
193 let Inst{25-0} = target;
196 //===----------------------------------------------------------------------===//
197 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
198 //===----------------------------------------------------------------------===//
199 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
207 let Inst{31-26} = op;
208 let Inst{25-21} = mfmt;
209 let Inst{20-16} = rt;
210 let Inst{15-11} = rd;
215 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
222 let Inst{31-26} = op;
223 let Inst{25-21} = rs;
224 let Inst{20-16} = rt;
225 let Inst{15-11} = rd;
227 let Inst{5-0} = funct;
230 class ADDI_FM<bits<6> op> : StdArch {
237 let Inst{31-26} = op;
238 let Inst{25-21} = rs;
239 let Inst{20-16} = rt;
240 let Inst{15-0} = imm16;
243 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
252 let Inst{21} = rotate;
253 let Inst{20-16} = rt;
254 let Inst{15-11} = rd;
255 let Inst{10-6} = shamt;
256 let Inst{5-0} = funct;
259 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
267 let Inst{25-21} = rs;
268 let Inst{20-16} = rt;
269 let Inst{15-11} = rd;
271 let Inst{6} = rotate;
272 let Inst{5-0} = funct;
275 class BEQ_FM<bits<6> op> : StdArch {
282 let Inst{31-26} = op;
283 let Inst{25-21} = rs;
284 let Inst{20-16} = rt;
285 let Inst{15-0} = offset;
288 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
294 let Inst{31-26} = op;
295 let Inst{25-21} = rs;
296 let Inst{20-16} = funct;
297 let Inst{15-0} = offset;
300 class BBIT_FM<bits<6> op> : StdArch {
307 let Inst{31-26} = op;
308 let Inst{25-21} = rs;
310 let Inst{15-0} = offset;
313 class SLTI_FM<bits<6> op> : StdArch {
320 let Inst{31-26} = op;
321 let Inst{25-21} = rs;
322 let Inst{20-16} = rt;
323 let Inst{15-0} = imm16;
326 class MFLO_FM<bits<6> funct> : StdArch {
333 let Inst{15-11} = rd;
335 let Inst{5-0} = funct;
338 class MTLO_FM<bits<6> funct> : StdArch {
344 let Inst{25-21} = rs;
346 let Inst{5-0} = funct;
349 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
355 let Inst{31-26} = 0x1f;
357 let Inst{20-16} = rt;
358 let Inst{15-11} = rd;
359 let Inst{10-6} = funct;
360 let Inst{5-0} = funct2;
363 class CLO_FM<bits<6> funct> : StdArch {
370 let Inst{31-26} = 0x1c;
371 let Inst{25-21} = rs;
372 let Inst{20-16} = rt;
373 let Inst{15-11} = rd;
375 let Inst{5-0} = funct;
379 class LUI_FM : StdArch {
385 let Inst{31-26} = 0xf;
387 let Inst{20-16} = rt;
388 let Inst{15-0} = imm16;
398 let Inst{25-21} = rs;
400 let Inst{15-11} = rd;
405 class BGEZAL_FM<bits<5> funct> : StdArch {
412 let Inst{25-21} = rs;
413 let Inst{20-16} = funct;
414 let Inst{15-0} = offset;
417 class SYNC_FM : StdArch {
423 let Inst{10-6} = stype;
427 class SYNCI_FM : StdArch {
428 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
430 bits<5> rs = addr{20-16};
431 bits<16> offset = addr{15-0};
435 let Inst{31-26} = 0b000001;
436 let Inst{25-21} = rs;
437 let Inst{20-16} = 0b11111;
438 let Inst{15-0} = offset;
441 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
447 let Inst{31-26} = op;
448 let Inst{25-21} = rs;
449 let Inst{20-16} = rt;
451 let Inst{5-0} = funct;
454 class EXT_FM<bits<6> funct> : StdArch {
462 let Inst{31-26} = 0x1f;
463 let Inst{25-21} = rs;
464 let Inst{20-16} = rt;
465 let Inst{15-11} = size;
466 let Inst{10-6} = pos;
467 let Inst{5-0} = funct;
470 class RDHWR_FM : StdArch {
476 let Inst{31-26} = 0x1f;
478 let Inst{20-16} = rt;
479 let Inst{15-11} = rd;
481 let Inst{5-0} = 0x3b;
484 class TEQ_FM<bits<6> funct> : StdArch {
492 let Inst{25-21} = rs;
493 let Inst{20-16} = rt;
494 let Inst{15-6} = code_;
495 let Inst{5-0} = funct;
498 class TEQI_FM<bits<5> funct> : StdArch {
505 let Inst{25-21} = rs;
506 let Inst{20-16} = funct;
507 let Inst{15-0} = imm16;
510 class WAIT_FM : StdArch {
513 let Inst{31-26} = 0x10;
516 let Inst{5-0} = 0x20;
519 class EXTS_FM<bits<6> funct> : StdArch {
527 let Inst{31-26} = 0x1c;
528 let Inst{25-21} = rs;
529 let Inst{20-16} = rt;
530 let Inst{15-11} = lenm1;
531 let Inst{10-6} = pos;
532 let Inst{5-0} = funct;
535 class MTMR_FM<bits<6> funct> : StdArch {
540 let Inst{31-26} = 0x1c;
541 let Inst{25-21} = rs;
543 let Inst{5-0} = funct;
546 class POP_FM<bits<6> funct> : StdArch {
552 let Inst{31-26} = 0x1c;
553 let Inst{25-21} = rs;
555 let Inst{15-11} = rd;
557 let Inst{5-0} = funct;
560 class SEQ_FM<bits<6> funct> : StdArch {
567 let Inst{31-26} = 0x1c;
568 let Inst{25-21} = rs;
569 let Inst{20-16} = rt;
570 let Inst{15-11} = rd;
572 let Inst{5-0} = funct;
575 class SEQI_FM<bits<6> funct> : StdArch {
582 let Inst{31-26} = 0x1c;
583 let Inst{25-21} = rs;
584 let Inst{20-16} = rt;
585 let Inst{15-6} = imm10;
586 let Inst{5-0} = funct;
589 //===----------------------------------------------------------------------===//
590 // System calls format <op|code_|funct>
591 //===----------------------------------------------------------------------===//
593 class SYS_FM<bits<6> funct> : StdArch
597 let Inst{31-26} = 0x0;
598 let Inst{25-6} = code_;
599 let Inst{5-0} = funct;
602 //===----------------------------------------------------------------------===//
603 // Break instruction format <op|code_1|funct>
604 //===----------------------------------------------------------------------===//
606 class BRK_FM<bits<6> funct> : StdArch
611 let Inst{31-26} = 0x0;
612 let Inst{25-16} = code_1;
613 let Inst{15-6} = code_2;
614 let Inst{5-0} = funct;
617 //===----------------------------------------------------------------------===//
618 // Exception return format <Cop0|1|0|funct>
619 //===----------------------------------------------------------------------===//
621 class ER_FM<bits<6> funct> : StdArch
624 let Inst{31-26} = 0x10;
627 let Inst{5-0} = funct;
631 //===----------------------------------------------------------------------===//
632 // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
633 //===----------------------------------------------------------------------===//
635 class EI_FM<bits<1> sc> : StdArch
639 let Inst{31-26} = 0x10;
640 let Inst{25-21} = 0xb;
641 let Inst{20-16} = rt;
642 let Inst{15-11} = 0xc;
648 //===----------------------------------------------------------------------===//
650 // FLOATING POINT INSTRUCTION FORMATS
652 // opcode - operation code.
654 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
655 // fd - dst reg, only used on 3 regs instr.
656 // fmt - double or single precision.
657 // funct - combined with opcode field give us an operation code.
659 //===----------------------------------------------------------------------===//
661 //===----------------------------------------------------------------------===//
662 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
663 //===----------------------------------------------------------------------===//
665 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
666 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
674 let Inst{25-21} = base;
675 let Inst{20-16} = ft;
676 let Inst{15-0} = imm16;
679 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
686 let Inst{31-26} = 0x11;
687 let Inst{25-21} = fmt;
688 let Inst{20-16} = ft;
689 let Inst{15-11} = fs;
691 let Inst{5-0} = funct;
694 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
700 let Inst{31-26} = 0x11;
701 let Inst{25-21} = fmt;
703 let Inst{15-11} = fs;
705 let Inst{5-0} = funct;
708 class MFC1_FM<bits<5> funct> : StdArch {
714 let Inst{31-26} = 0x11;
715 let Inst{25-21} = funct;
716 let Inst{20-16} = rt;
717 let Inst{15-11} = fs;
721 class LW_FM<bits<6> op> : StdArch {
727 let Inst{31-26} = op;
728 let Inst{25-21} = addr{20-16};
729 let Inst{20-16} = rt;
730 let Inst{15-0} = addr{15-0};
733 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
741 let Inst{31-26} = 0x13;
742 let Inst{25-21} = fr;
743 let Inst{20-16} = ft;
744 let Inst{15-11} = fs;
746 let Inst{5-3} = funct;
750 class LWXC1_FM<bits<6> funct> : StdArch {
757 let Inst{31-26} = 0x13;
758 let Inst{25-21} = base;
759 let Inst{20-16} = index;
762 let Inst{5-0} = funct;
765 class SWXC1_FM<bits<6> funct> : StdArch {
772 let Inst{31-26} = 0x13;
773 let Inst{25-21} = base;
774 let Inst{20-16} = index;
775 let Inst{15-11} = fs;
777 let Inst{5-0} = funct;
780 class BC1F_FM<bit nd, bit tf> : StdArch {
786 let Inst{31-26} = 0x11;
787 let Inst{25-21} = 0x8;
788 let Inst{20-18} = fcc;
791 let Inst{15-0} = offset;
794 class CEQS_FM<bits<5> fmt> : StdArch {
801 let Inst{31-26} = 0x11;
802 let Inst{25-21} = fmt;
803 let Inst{20-16} = ft;
804 let Inst{15-11} = fs;
805 let Inst{10-8} = 0; // cc
807 let Inst{3-0} = cond;
810 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
814 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
821 let Inst{31-26} = 0x11;
822 let Inst{25-21} = fmt;
823 let Inst{20-16} = rt;
824 let Inst{15-11} = fs;
826 let Inst{5-0} = funct;
829 class CMov_F_I_FM<bit tf> : StdArch {
837 let Inst{25-21} = rs;
838 let Inst{20-18} = fcc;
841 let Inst{15-11} = rd;
846 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
853 let Inst{31-26} = 0x11;
854 let Inst{25-21} = fmt;
855 let Inst{20-18} = fcc;
858 let Inst{15-11} = fs;
860 let Inst{5-0} = 0x11;
863 class BARRIER_FM<bits<5> op> : StdArch {
866 let Inst{31-26} = 0; // SPECIAL
868 let Inst{20-16} = 0; // rt = 0
869 let Inst{15-11} = 0; // rd = 0
870 let Inst{10-6} = op; // Operation
871 let Inst{5-0} = 0; // SLL
874 class SDBBP_FM : StdArch {
879 let Inst{31-26} = 0b011100; // SPECIAL2
880 let Inst{25-6} = code_;
881 let Inst{5-0} = 0b111111; // SDBBP
884 class JR_HB_FM<bits<6> op> : StdArch{
889 let Inst{31-26} = 0; // SPECIAL
890 let Inst{25-21} = rs;
897 class JALR_HB_FM<bits<6> op> : StdArch {
903 let Inst{31-26} = 0; // SPECIAL
904 let Inst{25-21} = rs;
906 let Inst{15-11} = rd;
912 class COP0_TLB_FM<bits<6> op> : StdArch {
915 let Inst{31-26} = 0x10; // COP0
916 let Inst{25} = 1; // CO
918 let Inst{5-0} = op; // Operation
921 class CACHEOP_FM<bits<6> op> : StdArch {
924 bits<5> base = addr{20-16};
925 bits<16> offset = addr{15-0};
929 let Inst{31-26} = op;
930 let Inst{25-21} = base;
931 let Inst{20-16} = hint;
932 let Inst{15-0} = offset;