1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
39 // Generic Mips Format
40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41 InstrItinClass itin, Format f>: Instruction
46 let Namespace = "Mips";
52 // Top 6 bits are the 'opcode' field
53 let Inst{31-26} = Opcode;
55 let OutOperandList = outs;
56 let InOperandList = ins;
58 let AsmString = asmstr;
59 let Pattern = pattern;
63 // Attributes specific to Mips instructions...
65 bits<4> FormBits = Form.Value;
67 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68 let TSFlags{3-0} = FormBits;
70 let DecoderNamespace = "Mips";
72 field bits<32> SoftFail = 0;
75 // Mips32/64 Instruction Format
76 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77 InstrItinClass itin, Format f>:
78 MipsInst<outs, ins, asmstr, pattern, itin, f> {
79 let Predicates = [HasStandardEncoding];
82 // Mips Pseudo Instructions Format
83 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
84 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
85 let isCodeGenOnly = 1;
89 // Mips32/64 Pseudo Instruction Format
90 class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>:
91 MipsPseudo<outs, ins, asmstr, pattern> {
92 let Predicates = [HasStandardEncoding];
95 //===----------------------------------------------------------------------===//
96 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
97 //===----------------------------------------------------------------------===//
99 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
100 list<dag> pattern, InstrItinClass itin>:
101 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
112 let Inst{25-21} = rs;
113 let Inst{20-16} = rt;
114 let Inst{15-11} = rd;
115 let Inst{10-6} = shamt;
116 let Inst{5-0} = funct;
119 //===----------------------------------------------------------------------===//
120 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
121 //===----------------------------------------------------------------------===//
123 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
124 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
132 let Inst{25-21} = rs;
133 let Inst{20-16} = rt;
134 let Inst{15-0} = imm16;
137 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
138 list<dag> pattern, InstrItinClass itin>:
139 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
147 let Inst{25-21} = rs;
148 let Inst{20-16} = rt;
149 let Inst{15-0} = imm16;
152 //===----------------------------------------------------------------------===//
153 // Format J instruction class in Mips : <|opcode|address|>
154 //===----------------------------------------------------------------------===//
156 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
157 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
163 let Inst{25-0} = addr;
166 //===----------------------------------------------------------------------===//
168 // FLOATING POINT INSTRUCTION FORMATS
170 // opcode - operation code.
172 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
173 // fd - dst reg, only used on 3 regs instr.
174 // fmt - double or single precision.
175 // funct - combined with opcode field give us an operation code.
177 //===----------------------------------------------------------------------===//
179 //===----------------------------------------------------------------------===//
180 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
181 //===----------------------------------------------------------------------===//
183 class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
184 string asmstr, list<dag> pattern> :
185 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFR>
197 let Inst{25-21} = fmt;
198 let Inst{20-16} = ft;
199 let Inst{15-11} = fs;
201 let Inst{5-0} = funct;
204 //===----------------------------------------------------------------------===//
205 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
206 //===----------------------------------------------------------------------===//
208 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
209 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
217 let Inst{25-21} = base;
218 let Inst{20-16} = ft;
219 let Inst{15-0} = imm16;
222 //===----------------------------------------------------------------------===//
223 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
224 //===----------------------------------------------------------------------===//
226 class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
227 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
237 let Inst{25-21} = fmt;
238 let Inst{20-16} = ft;
239 let Inst{15-11} = fs;
241 let Inst{5-4} = 0b11;
246 class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
248 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
258 let Inst{25-21} = rs;
259 let Inst{20-18} = cc;
262 let Inst{15-11} = rd;
267 class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
269 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
281 let Inst{25-21} = fmt;
282 let Inst{20-18} = cc;
285 let Inst{15-11} = fs;
290 // FP unary instructions without patterns.
291 class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
292 RegisterClass DstRC, RegisterClass SrcRC> :
293 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
294 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
298 // FP unary instructions with patterns.
299 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
300 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
301 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
302 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
303 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
307 class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
308 string fmtstr, RegisterClass RC, SDNode OpNode> :
309 FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
310 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
311 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
313 // Floating point madd/msub/nmadd/nmsub.
314 class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
316 : InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> {
323 let Inst{25-21} = fr;
324 let Inst{20-16} = ft;
325 let Inst{15-11} = fs;
327 let Inst{5-3} = funct;
331 // FP indexed load/store instructions.
332 class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr,
334 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
343 let Inst{25-21} = base;
344 let Inst{20-16} = index;
345 let Inst{15-11} = fs;
347 let Inst{5-0} = funct;