1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
55 def Std2MicroMipsR6 : InstrMapping {
56 let FilterClass = "StdMMR6Rel";
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
59 // Instructions with the same predicate sense form a column.
60 let ColFields = ["Arch"];
61 // The key column is the unpredicated instructions.
63 // Value columns are PredSense=true and PredSense=false
64 let ValueCols = [["se"], ["micromipsr6"]];
71 // Generic Mips Format
72 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
73 InstrItinClass itin, Format f>: Instruction
78 let Namespace = "Mips";
84 // Top 6 bits are the 'opcode' field
85 let Inst{31-26} = Opcode;
87 let OutOperandList = outs;
88 let InOperandList = ins;
90 let AsmString = asmstr;
91 let Pattern = pattern;
95 // Attributes specific to Mips instructions...
97 bits<4> FormBits = Form.Value;
99 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
100 let TSFlags{3-0} = FormBits;
102 let DecoderNamespace = "Mips";
104 field bits<32> SoftFail = 0;
107 // Mips32/64 Instruction Format
108 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
109 InstrItinClass itin, Format f, string opstr = ""> :
110 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
111 let EncodingPredicates = [HasStdEnc];
112 string BaseOpcode = opstr;
116 // Mips Pseudo Instructions Format
117 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
118 InstrItinClass itin = IIPseudo> :
119 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
120 let isCodeGenOnly = 1;
124 // Mips32/64 Pseudo Instruction Format
125 class PseudoSE<dag outs, dag ins, list<dag> pattern,
126 InstrItinClass itin = IIPseudo> :
127 MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
128 let EncodingPredicates = [HasStdEnc];
131 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
132 // These are aliases that require C++ handling to convert to the target
133 // instruction, while InstAliases can be handled directly by tblgen.
134 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
135 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
139 //===----------------------------------------------------------------------===//
140 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
141 //===----------------------------------------------------------------------===//
143 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
144 list<dag> pattern, InstrItinClass itin>:
145 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
156 let Inst{25-21} = rs;
157 let Inst{20-16} = rt;
158 let Inst{15-11} = rd;
159 let Inst{10-6} = shamt;
160 let Inst{5-0} = funct;
163 //===----------------------------------------------------------------------===//
164 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
165 //===----------------------------------------------------------------------===//
167 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
168 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
176 let Inst{25-21} = rs;
177 let Inst{20-16} = rt;
178 let Inst{15-0} = imm16;
181 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
182 list<dag> pattern, InstrItinClass itin>:
183 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
191 let Inst{25-21} = rs;
192 let Inst{20-16} = rt;
193 let Inst{15-0} = imm16;
196 //===----------------------------------------------------------------------===//
197 // Format J instruction class in Mips : <|opcode|address|>
198 //===----------------------------------------------------------------------===//
200 class FJ<bits<6> op> : StdArch
206 let Inst{31-26} = op;
207 let Inst{25-0} = target;
210 //===----------------------------------------------------------------------===//
211 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
212 //===----------------------------------------------------------------------===//
213 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
221 let Inst{31-26} = op;
222 let Inst{25-21} = mfmt;
223 let Inst{20-16} = rt;
224 let Inst{15-11} = rd;
229 class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
235 let Inst{31-26} = op;
236 let Inst{25-21} = mfmt;
237 let Inst{20-16} = rt;
238 let Inst{15-0} = imm16;
241 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
248 let Inst{31-26} = op;
249 let Inst{25-21} = rs;
250 let Inst{20-16} = rt;
251 let Inst{15-11} = rd;
253 let Inst{5-0} = funct;
256 class ADDI_FM<bits<6> op> : StdArch {
263 let Inst{31-26} = op;
264 let Inst{25-21} = rs;
265 let Inst{20-16} = rt;
266 let Inst{15-0} = imm16;
269 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
278 let Inst{21} = rotate;
279 let Inst{20-16} = rt;
280 let Inst{15-11} = rd;
281 let Inst{10-6} = shamt;
282 let Inst{5-0} = funct;
285 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
293 let Inst{25-21} = rs;
294 let Inst{20-16} = rt;
295 let Inst{15-11} = rd;
297 let Inst{6} = rotate;
298 let Inst{5-0} = funct;
301 class BEQ_FM<bits<6> op> : StdArch {
308 let Inst{31-26} = op;
309 let Inst{25-21} = rs;
310 let Inst{20-16} = rt;
311 let Inst{15-0} = offset;
314 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
320 let Inst{31-26} = op;
321 let Inst{25-21} = rs;
322 let Inst{20-16} = funct;
323 let Inst{15-0} = offset;
326 class BBIT_FM<bits<6> op> : StdArch {
333 let Inst{31-26} = op;
334 let Inst{25-21} = rs;
336 let Inst{15-0} = offset;
339 class SLTI_FM<bits<6> op> : StdArch {
346 let Inst{31-26} = op;
347 let Inst{25-21} = rs;
348 let Inst{20-16} = rt;
349 let Inst{15-0} = imm16;
352 class MFLO_FM<bits<6> funct> : StdArch {
359 let Inst{15-11} = rd;
361 let Inst{5-0} = funct;
364 class MTLO_FM<bits<6> funct> : StdArch {
370 let Inst{25-21} = rs;
372 let Inst{5-0} = funct;
375 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
381 let Inst{31-26} = 0x1f;
383 let Inst{20-16} = rt;
384 let Inst{15-11} = rd;
385 let Inst{10-6} = funct;
386 let Inst{5-0} = funct2;
389 class CLO_FM<bits<6> funct> : StdArch {
396 let Inst{31-26} = 0x1c;
397 let Inst{25-21} = rs;
398 let Inst{20-16} = rt;
399 let Inst{15-11} = rd;
401 let Inst{5-0} = funct;
405 class LUI_FM : StdArch {
411 let Inst{31-26} = 0xf;
413 let Inst{20-16} = rt;
414 let Inst{15-0} = imm16;
424 let Inst{25-21} = rs;
426 let Inst{15-11} = rd;
431 class BGEZAL_FM<bits<5> funct> : StdArch {
438 let Inst{25-21} = rs;
439 let Inst{20-16} = funct;
440 let Inst{15-0} = offset;
443 class SYNC_FM : StdArch {
449 let Inst{10-6} = stype;
453 class SYNCI_FM : StdArch {
454 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
456 bits<5> rs = addr{20-16};
457 bits<16> offset = addr{15-0};
461 let Inst{31-26} = 0b000001;
462 let Inst{25-21} = rs;
463 let Inst{20-16} = 0b11111;
464 let Inst{15-0} = offset;
467 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
473 let Inst{31-26} = op;
474 let Inst{25-21} = rs;
475 let Inst{20-16} = rt;
477 let Inst{5-0} = funct;
480 class EXT_FM<bits<6> funct> : StdArch {
488 let Inst{31-26} = 0x1f;
489 let Inst{25-21} = rs;
490 let Inst{20-16} = rt;
491 let Inst{15-11} = size;
492 let Inst{10-6} = pos;
493 let Inst{5-0} = funct;
496 class RDHWR_FM : StdArch {
502 let Inst{31-26} = 0x1f;
504 let Inst{20-16} = rt;
505 let Inst{15-11} = rd;
507 let Inst{5-0} = 0x3b;
510 class TEQ_FM<bits<6> funct> : StdArch {
518 let Inst{25-21} = rs;
519 let Inst{20-16} = rt;
520 let Inst{15-6} = code_;
521 let Inst{5-0} = funct;
524 class TEQI_FM<bits<5> funct> : StdArch {
531 let Inst{25-21} = rs;
532 let Inst{20-16} = funct;
533 let Inst{15-0} = imm16;
536 class WAIT_FM : StdArch {
539 let Inst{31-26} = 0x10;
542 let Inst{5-0} = 0x20;
545 class EXTS_FM<bits<6> funct> : StdArch {
553 let Inst{31-26} = 0x1c;
554 let Inst{25-21} = rs;
555 let Inst{20-16} = rt;
556 let Inst{15-11} = lenm1;
557 let Inst{10-6} = pos;
558 let Inst{5-0} = funct;
561 class MTMR_FM<bits<6> funct> : StdArch {
566 let Inst{31-26} = 0x1c;
567 let Inst{25-21} = rs;
569 let Inst{5-0} = funct;
572 class POP_FM<bits<6> funct> : StdArch {
578 let Inst{31-26} = 0x1c;
579 let Inst{25-21} = rs;
581 let Inst{15-11} = rd;
583 let Inst{5-0} = funct;
586 class SEQ_FM<bits<6> funct> : StdArch {
593 let Inst{31-26} = 0x1c;
594 let Inst{25-21} = rs;
595 let Inst{20-16} = rt;
596 let Inst{15-11} = rd;
598 let Inst{5-0} = funct;
601 class SEQI_FM<bits<6> funct> : StdArch {
608 let Inst{31-26} = 0x1c;
609 let Inst{25-21} = rs;
610 let Inst{20-16} = rt;
611 let Inst{15-6} = imm10;
612 let Inst{5-0} = funct;
615 //===----------------------------------------------------------------------===//
616 // System calls format <op|code_|funct>
617 //===----------------------------------------------------------------------===//
619 class SYS_FM<bits<6> funct> : StdArch
623 let Inst{31-26} = 0x0;
624 let Inst{25-6} = code_;
625 let Inst{5-0} = funct;
628 //===----------------------------------------------------------------------===//
629 // Break instruction format <op|code_1|funct>
630 //===----------------------------------------------------------------------===//
632 class BRK_FM<bits<6> funct> : StdArch
637 let Inst{31-26} = 0x0;
638 let Inst{25-16} = code_1;
639 let Inst{15-6} = code_2;
640 let Inst{5-0} = funct;
643 //===----------------------------------------------------------------------===//
644 // Exception return format <Cop0|1|0|funct>
645 //===----------------------------------------------------------------------===//
647 class ER_FM<bits<6> funct, bit LLBit> : StdArch
650 let Inst{31-26} = 0x10;
654 let Inst{5-0} = funct;
657 //===----------------------------------------------------------------------===//
658 // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
659 //===----------------------------------------------------------------------===//
661 class EI_FM<bits<1> sc> : StdArch
665 let Inst{31-26} = 0x10;
666 let Inst{25-21} = 0xb;
667 let Inst{20-16} = rt;
668 let Inst{15-11} = 0xc;
674 //===----------------------------------------------------------------------===//
676 // FLOATING POINT INSTRUCTION FORMATS
678 // opcode - operation code.
680 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
681 // fd - dst reg, only used on 3 regs instr.
682 // fmt - double or single precision.
683 // funct - combined with opcode field give us an operation code.
685 //===----------------------------------------------------------------------===//
687 //===----------------------------------------------------------------------===//
688 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
689 //===----------------------------------------------------------------------===//
691 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
692 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
700 let Inst{25-21} = base;
701 let Inst{20-16} = ft;
702 let Inst{15-0} = imm16;
705 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
712 let Inst{31-26} = 0x11;
713 let Inst{25-21} = fmt;
714 let Inst{20-16} = ft;
715 let Inst{15-11} = fs;
717 let Inst{5-0} = funct;
720 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
726 let Inst{31-26} = 0x11;
727 let Inst{25-21} = fmt;
729 let Inst{15-11} = fs;
731 let Inst{5-0} = funct;
734 class MFC1_FM<bits<5> funct> : StdArch {
740 let Inst{31-26} = 0x11;
741 let Inst{25-21} = funct;
742 let Inst{20-16} = rt;
743 let Inst{15-11} = fs;
747 class LW_FM<bits<6> op> : StdArch {
753 let Inst{31-26} = op;
754 let Inst{25-21} = addr{20-16};
755 let Inst{20-16} = rt;
756 let Inst{15-0} = addr{15-0};
759 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
767 let Inst{31-26} = 0x13;
768 let Inst{25-21} = fr;
769 let Inst{20-16} = ft;
770 let Inst{15-11} = fs;
772 let Inst{5-3} = funct;
776 class LWXC1_FM<bits<6> funct> : StdArch {
783 let Inst{31-26} = 0x13;
784 let Inst{25-21} = base;
785 let Inst{20-16} = index;
788 let Inst{5-0} = funct;
791 class SWXC1_FM<bits<6> funct> : StdArch {
798 let Inst{31-26} = 0x13;
799 let Inst{25-21} = base;
800 let Inst{20-16} = index;
801 let Inst{15-11} = fs;
803 let Inst{5-0} = funct;
806 class BC1F_FM<bit nd, bit tf> : StdArch {
812 let Inst{31-26} = 0x11;
813 let Inst{25-21} = 0x8;
814 let Inst{20-18} = fcc;
817 let Inst{15-0} = offset;
820 class CEQS_FM<bits<5> fmt> : StdArch {
827 let Inst{31-26} = 0x11;
828 let Inst{25-21} = fmt;
829 let Inst{20-16} = ft;
830 let Inst{15-11} = fs;
831 let Inst{10-8} = 0; // cc
833 let Inst{3-0} = cond;
836 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
840 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
847 let Inst{31-26} = 0x11;
848 let Inst{25-21} = fmt;
849 let Inst{20-16} = rt;
850 let Inst{15-11} = fs;
852 let Inst{5-0} = funct;
855 class CMov_F_I_FM<bit tf> : StdArch {
863 let Inst{25-21} = rs;
864 let Inst{20-18} = fcc;
867 let Inst{15-11} = rd;
872 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
879 let Inst{31-26} = 0x11;
880 let Inst{25-21} = fmt;
881 let Inst{20-18} = fcc;
884 let Inst{15-11} = fs;
886 let Inst{5-0} = 0x11;
889 class BARRIER_FM<bits<5> op> : StdArch {
892 let Inst{31-26} = 0; // SPECIAL
894 let Inst{20-16} = 0; // rt = 0
895 let Inst{15-11} = 0; // rd = 0
896 let Inst{10-6} = op; // Operation
897 let Inst{5-0} = 0; // SLL
900 class SDBBP_FM : StdArch {
905 let Inst{31-26} = 0b011100; // SPECIAL2
906 let Inst{25-6} = code_;
907 let Inst{5-0} = 0b111111; // SDBBP
910 class JR_HB_FM<bits<6> op> : StdArch{
915 let Inst{31-26} = 0; // SPECIAL
916 let Inst{25-21} = rs;
923 class JALR_HB_FM<bits<6> op> : StdArch {
929 let Inst{31-26} = 0; // SPECIAL
930 let Inst{25-21} = rs;
932 let Inst{15-11} = rd;
938 class COP0_TLB_FM<bits<6> op> : StdArch {
941 let Inst{31-26} = 0x10; // COP0
942 let Inst{25} = 1; // CO
944 let Inst{5-0} = op; // Operation
947 class CACHEOP_FM<bits<6> op> : StdArch {
950 bits<5> base = addr{20-16};
951 bits<16> offset = addr{15-0};
955 let Inst{31-26} = op;
956 let Inst{25-21} = base;
957 let Inst{20-16} = hint;
958 let Inst{15-0} = offset;