1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
57 // Generic Mips Format
58 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
59 InstrItinClass itin, Format f>: Instruction
64 let Namespace = "Mips";
70 // Top 6 bits are the 'opcode' field
71 let Inst{31-26} = Opcode;
73 let OutOperandList = outs;
74 let InOperandList = ins;
76 let AsmString = asmstr;
77 let Pattern = pattern;
81 // Attributes specific to Mips instructions...
83 bits<4> FormBits = Form.Value;
85 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
86 let TSFlags{3-0} = FormBits;
88 let DecoderNamespace = "Mips";
90 field bits<32> SoftFail = 0;
93 // Mips32/64 Instruction Format
94 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
95 InstrItinClass itin, Format f, string opstr = ""> :
96 MipsInst<outs, ins, asmstr, pattern, itin, f> {
97 let Predicates = [HasStdEnc];
98 string BaseOpcode = opstr;
102 // Mips Pseudo Instructions Format
103 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
104 InstrItinClass itin = IIPseudo> :
105 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
106 let isCodeGenOnly = 1;
110 // Mips32/64 Pseudo Instruction Format
111 class PseudoSE<dag outs, dag ins, list<dag> pattern,
112 InstrItinClass itin = IIPseudo>:
113 MipsPseudo<outs, ins, pattern, itin> {
114 let Predicates = [HasStdEnc];
117 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
118 // These are aliases that require C++ handling to convert to the target
119 // instruction, while InstAliases can be handled directly by tblgen.
120 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
125 //===----------------------------------------------------------------------===//
126 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
127 //===----------------------------------------------------------------------===//
129 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
130 list<dag> pattern, InstrItinClass itin>:
131 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
142 let Inst{25-21} = rs;
143 let Inst{20-16} = rt;
144 let Inst{15-11} = rd;
145 let Inst{10-6} = shamt;
146 let Inst{5-0} = funct;
149 //===----------------------------------------------------------------------===//
150 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
151 //===----------------------------------------------------------------------===//
153 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
162 let Inst{25-21} = rs;
163 let Inst{20-16} = rt;
164 let Inst{15-0} = imm16;
167 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
168 list<dag> pattern, InstrItinClass itin>:
169 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
177 let Inst{25-21} = rs;
178 let Inst{20-16} = rt;
179 let Inst{15-0} = imm16;
182 //===----------------------------------------------------------------------===//
183 // Format J instruction class in Mips : <|opcode|address|>
184 //===----------------------------------------------------------------------===//
192 let Inst{31-26} = op;
193 let Inst{25-0} = target;
196 //===----------------------------------------------------------------------===//
197 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
198 //===----------------------------------------------------------------------===//
199 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
207 let Inst{31-26} = op;
208 let Inst{25-21} = mfmt;
209 let Inst{20-16} = rt;
210 let Inst{15-11} = rd;
215 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
222 let Inst{31-26} = op;
223 let Inst{25-21} = rs;
224 let Inst{20-16} = rt;
225 let Inst{15-11} = rd;
227 let Inst{5-0} = funct;
230 class ADDI_FM<bits<6> op> : StdArch {
237 let Inst{31-26} = op;
238 let Inst{25-21} = rs;
239 let Inst{20-16} = rt;
240 let Inst{15-0} = imm16;
243 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
252 let Inst{21} = rotate;
253 let Inst{20-16} = rt;
254 let Inst{15-11} = rd;
255 let Inst{10-6} = shamt;
256 let Inst{5-0} = funct;
259 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
267 let Inst{25-21} = rs;
268 let Inst{20-16} = rt;
269 let Inst{15-11} = rd;
271 let Inst{6} = rotate;
272 let Inst{5-0} = funct;
275 class BEQ_FM<bits<6> op> {
282 let Inst{31-26} = op;
283 let Inst{25-21} = rs;
284 let Inst{20-16} = rt;
285 let Inst{15-0} = offset;
288 class BGEZ_FM<bits<6> op, bits<5> funct> {
294 let Inst{31-26} = op;
295 let Inst{25-21} = rs;
296 let Inst{20-16} = funct;
297 let Inst{15-0} = offset;
308 let Inst{15-0} = offset;
311 class SLTI_FM<bits<6> op> : StdArch {
318 let Inst{31-26} = op;
319 let Inst{25-21} = rs;
320 let Inst{20-16} = rt;
321 let Inst{15-0} = imm16;
324 class MFLO_FM<bits<6> funct> {
331 let Inst{15-11} = rd;
333 let Inst{5-0} = funct;
336 class MTLO_FM<bits<6> funct> {
342 let Inst{25-21} = rs;
344 let Inst{5-0} = funct;
347 class SEB_FM<bits<5> funct, bits<6> funct2> {
353 let Inst{31-26} = 0x1f;
355 let Inst{20-16} = rt;
356 let Inst{15-11} = rd;
357 let Inst{10-6} = funct;
358 let Inst{5-0} = funct2;
361 class CLO_FM<bits<6> funct> {
368 let Inst{31-26} = 0x1c;
369 let Inst{25-21} = rs;
370 let Inst{20-16} = rt;
371 let Inst{15-11} = rd;
373 let Inst{5-0} = funct;
383 let Inst{31-26} = 0xf;
385 let Inst{20-16} = rt;
386 let Inst{15-0} = imm16;
396 let Inst{25-21} = rs;
398 let Inst{15-11} = rd;
410 let Inst{20-16} = 0x11;
411 let Inst{15-0} = offset;
414 class BGEZAL_FM<bits<5> funct> {
421 let Inst{25-21} = rs;
422 let Inst{20-16} = funct;
423 let Inst{15-0} = offset;
432 let Inst{10-6} = stype;
436 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
442 let Inst{31-26} = op;
443 let Inst{25-21} = rs;
444 let Inst{20-16} = rt;
446 let Inst{5-0} = funct;
449 class EXT_FM<bits<6> funct> {
457 let Inst{31-26} = 0x1f;
458 let Inst{25-21} = rs;
459 let Inst{20-16} = rt;
460 let Inst{15-11} = size;
461 let Inst{10-6} = pos;
462 let Inst{5-0} = funct;
471 let Inst{31-26} = 0x1f;
473 let Inst{20-16} = rt;
474 let Inst{15-11} = rd;
476 let Inst{5-0} = 0x3b;
479 class TEQ_FM<bits<6> funct> {
487 let Inst{25-21} = rs;
488 let Inst{20-16} = rt;
489 let Inst{15-6} = code_;
490 let Inst{5-0} = funct;
493 //===----------------------------------------------------------------------===//
494 // System calls format <op|code_|funct>
495 //===----------------------------------------------------------------------===//
497 class SYS_FM<bits<6> funct>
501 let Inst{31-26} = 0x0;
502 let Inst{25-6} = code_;
503 let Inst{5-0} = funct;
506 //===----------------------------------------------------------------------===//
507 // Break instruction format <op|code_1|funct>
508 //===----------------------------------------------------------------------===//
510 class BRK_FM<bits<6> funct>
515 let Inst{31-26} = 0x0;
516 let Inst{25-16} = code_1;
517 let Inst{15-6} = code_2;
518 let Inst{5-0} = funct;
521 //===----------------------------------------------------------------------===//
523 // FLOATING POINT INSTRUCTION FORMATS
525 // opcode - operation code.
527 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
528 // fd - dst reg, only used on 3 regs instr.
529 // fmt - double or single precision.
530 // funct - combined with opcode field give us an operation code.
532 //===----------------------------------------------------------------------===//
534 //===----------------------------------------------------------------------===//
535 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
536 //===----------------------------------------------------------------------===//
538 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
539 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
547 let Inst{25-21} = base;
548 let Inst{20-16} = ft;
549 let Inst{15-0} = imm16;
552 class ADDS_FM<bits<6> funct, bits<5> fmt> {
559 let Inst{31-26} = 0x11;
560 let Inst{25-21} = fmt;
561 let Inst{20-16} = ft;
562 let Inst{15-11} = fs;
564 let Inst{5-0} = funct;
567 class ABSS_FM<bits<6> funct, bits<5> fmt> {
573 let Inst{31-26} = 0x11;
574 let Inst{25-21} = fmt;
576 let Inst{15-11} = fs;
578 let Inst{5-0} = funct;
581 class MFC1_FM<bits<5> funct> {
587 let Inst{31-26} = 0x11;
588 let Inst{25-21} = funct;
589 let Inst{20-16} = rt;
590 let Inst{15-11} = fs;
594 class LW_FM<bits<6> op> : StdArch {
600 let Inst{31-26} = op;
601 let Inst{25-21} = addr{20-16};
602 let Inst{20-16} = rt;
603 let Inst{15-0} = addr{15-0};
606 class MADDS_FM<bits<3> funct, bits<3> fmt> {
614 let Inst{31-26} = 0x13;
615 let Inst{25-21} = fr;
616 let Inst{20-16} = ft;
617 let Inst{15-11} = fs;
619 let Inst{5-3} = funct;
623 class LWXC1_FM<bits<6> funct> {
630 let Inst{31-26} = 0x13;
631 let Inst{25-21} = base;
632 let Inst{20-16} = index;
635 let Inst{5-0} = funct;
638 class SWXC1_FM<bits<6> funct> {
645 let Inst{31-26} = 0x13;
646 let Inst{25-21} = base;
647 let Inst{20-16} = index;
648 let Inst{15-11} = fs;
650 let Inst{5-0} = funct;
653 class BC1F_FM<bit nd, bit tf> {
658 let Inst{31-26} = 0x11;
659 let Inst{25-21} = 0x8;
660 let Inst{20-18} = 0; // cc
663 let Inst{15-0} = offset;
666 class CEQS_FM<bits<5> fmt> {
673 let Inst{31-26} = 0x11;
674 let Inst{25-21} = fmt;
675 let Inst{20-16} = ft;
676 let Inst{15-11} = fs;
677 let Inst{10-8} = 0; // cc
679 let Inst{3-0} = cond;
682 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
689 let Inst{31-26} = 0x11;
690 let Inst{25-21} = fmt;
691 let Inst{20-16} = rt;
692 let Inst{15-11} = fs;
694 let Inst{5-0} = funct;
697 class CMov_F_I_FM<bit tf> {
704 let Inst{25-21} = rs;
705 let Inst{20-18} = 0; // cc
708 let Inst{15-11} = rd;
713 class CMov_F_F_FM<bits<5> fmt, bit tf> {
719 let Inst{31-26} = 0x11;
720 let Inst{25-21} = fmt;
721 let Inst{20-18} = 0; // cc
724 let Inst{15-11} = fs;
726 let Inst{5-0} = 0x11;