1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
41 def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
57 // Generic Mips Format
58 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
59 InstrItinClass itin, Format f>: Instruction
64 let Namespace = "Mips";
70 // Top 6 bits are the 'opcode' field
71 let Inst{31-26} = Opcode;
73 let OutOperandList = outs;
74 let InOperandList = ins;
76 let AsmString = asmstr;
77 let Pattern = pattern;
81 // Attributes specific to Mips instructions...
83 bits<4> FormBits = Form.Value;
85 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
86 let TSFlags{3-0} = FormBits;
88 let DecoderNamespace = "Mips";
90 field bits<32> SoftFail = 0;
93 // Mips32/64 Instruction Format
94 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
95 InstrItinClass itin, Format f, string opstr = ""> :
96 MipsInst<outs, ins, asmstr, pattern, itin, f> {
97 let Predicates = [HasStdEnc];
98 string BaseOpcode = opstr;
100 let MnemonicContainsDot = 1;
103 // Mips Pseudo Instructions Format
104 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
105 InstrItinClass itin = IIPseudo> :
106 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
107 let isCodeGenOnly = 1;
111 // Mips32/64 Pseudo Instruction Format
112 class PseudoSE<dag outs, dag ins, list<dag> pattern,
113 InstrItinClass itin = IIPseudo>:
114 MipsPseudo<outs, ins, pattern, itin> {
115 let Predicates = [HasStdEnc];
118 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
119 // These are aliases that require C++ handling to convert to the target
120 // instruction, while InstAliases can be handled directly by tblgen.
121 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
122 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
126 //===----------------------------------------------------------------------===//
127 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
128 //===----------------------------------------------------------------------===//
130 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
131 list<dag> pattern, InstrItinClass itin>:
132 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
143 let Inst{25-21} = rs;
144 let Inst{20-16} = rt;
145 let Inst{15-11} = rd;
146 let Inst{10-6} = shamt;
147 let Inst{5-0} = funct;
150 //===----------------------------------------------------------------------===//
151 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
152 //===----------------------------------------------------------------------===//
154 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
155 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
163 let Inst{25-21} = rs;
164 let Inst{20-16} = rt;
165 let Inst{15-0} = imm16;
168 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
169 list<dag> pattern, InstrItinClass itin>:
170 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
178 let Inst{25-21} = rs;
179 let Inst{20-16} = rt;
180 let Inst{15-0} = imm16;
183 //===----------------------------------------------------------------------===//
184 // Format J instruction class in Mips : <|opcode|address|>
185 //===----------------------------------------------------------------------===//
193 let Inst{31-26} = op;
194 let Inst{25-0} = target;
197 //===----------------------------------------------------------------------===//
198 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
199 //===----------------------------------------------------------------------===//
200 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
208 let Inst{31-26} = op;
209 let Inst{25-21} = mfmt;
210 let Inst{20-16} = rt;
211 let Inst{15-11} = rd;
216 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
223 let Inst{31-26} = op;
224 let Inst{25-21} = rs;
225 let Inst{20-16} = rt;
226 let Inst{15-11} = rd;
228 let Inst{5-0} = funct;
231 class ADDI_FM<bits<6> op> : StdArch {
238 let Inst{31-26} = op;
239 let Inst{25-21} = rs;
240 let Inst{20-16} = rt;
241 let Inst{15-0} = imm16;
244 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
253 let Inst{21} = rotate;
254 let Inst{20-16} = rt;
255 let Inst{15-11} = rd;
256 let Inst{10-6} = shamt;
257 let Inst{5-0} = funct;
260 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
268 let Inst{25-21} = rs;
269 let Inst{20-16} = rt;
270 let Inst{15-11} = rd;
272 let Inst{6} = rotate;
273 let Inst{5-0} = funct;
276 class BEQ_FM<bits<6> op> {
283 let Inst{31-26} = op;
284 let Inst{25-21} = rs;
285 let Inst{20-16} = rt;
286 let Inst{15-0} = offset;
289 class BGEZ_FM<bits<6> op, bits<5> funct> {
295 let Inst{31-26} = op;
296 let Inst{25-21} = rs;
297 let Inst{20-16} = funct;
298 let Inst{15-0} = offset;
309 let Inst{15-0} = offset;
312 class SLTI_FM<bits<6> op> : StdArch {
319 let Inst{31-26} = op;
320 let Inst{25-21} = rs;
321 let Inst{20-16} = rt;
322 let Inst{15-0} = imm16;
325 class MFLO_FM<bits<6> funct> {
332 let Inst{15-11} = rd;
334 let Inst{5-0} = funct;
337 class MTLO_FM<bits<6> funct> {
343 let Inst{25-21} = rs;
345 let Inst{5-0} = funct;
348 class SEB_FM<bits<5> funct, bits<6> funct2> {
354 let Inst{31-26} = 0x1f;
356 let Inst{20-16} = rt;
357 let Inst{15-11} = rd;
358 let Inst{10-6} = funct;
359 let Inst{5-0} = funct2;
362 class CLO_FM<bits<6> funct> {
369 let Inst{31-26} = 0x1c;
370 let Inst{25-21} = rs;
371 let Inst{20-16} = rt;
372 let Inst{15-11} = rd;
374 let Inst{5-0} = funct;
384 let Inst{31-26} = 0xf;
386 let Inst{20-16} = rt;
387 let Inst{15-0} = imm16;
397 let Inst{25-21} = rs;
399 let Inst{15-11} = rd;
404 class BGEZAL_FM<bits<5> funct> {
411 let Inst{25-21} = rs;
412 let Inst{20-16} = funct;
413 let Inst{15-0} = offset;
422 let Inst{10-6} = stype;
426 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
432 let Inst{31-26} = op;
433 let Inst{25-21} = rs;
434 let Inst{20-16} = rt;
436 let Inst{5-0} = funct;
439 class EXT_FM<bits<6> funct> {
447 let Inst{31-26} = 0x1f;
448 let Inst{25-21} = rs;
449 let Inst{20-16} = rt;
450 let Inst{15-11} = size;
451 let Inst{10-6} = pos;
452 let Inst{5-0} = funct;
461 let Inst{31-26} = 0x1f;
463 let Inst{20-16} = rt;
464 let Inst{15-11} = rd;
466 let Inst{5-0} = 0x3b;
469 class TEQ_FM<bits<6> funct> {
477 let Inst{25-21} = rs;
478 let Inst{20-16} = rt;
479 let Inst{15-6} = code_;
480 let Inst{5-0} = funct;
483 //===----------------------------------------------------------------------===//
484 // System calls format <op|code_|funct>
485 //===----------------------------------------------------------------------===//
487 class SYS_FM<bits<6> funct>
491 let Inst{31-26} = 0x0;
492 let Inst{25-6} = code_;
493 let Inst{5-0} = funct;
496 //===----------------------------------------------------------------------===//
497 // Break instruction format <op|code_1|funct>
498 //===----------------------------------------------------------------------===//
500 class BRK_FM<bits<6> funct>
505 let Inst{31-26} = 0x0;
506 let Inst{25-16} = code_1;
507 let Inst{15-6} = code_2;
508 let Inst{5-0} = funct;
511 //===----------------------------------------------------------------------===//
512 // Exception return format <Cop0|1|0|funct>
513 //===----------------------------------------------------------------------===//
515 class ER_FM<bits<6> funct>
518 let Inst{31-26} = 0x10;
521 let Inst{5-0} = funct;
524 //===----------------------------------------------------------------------===//
526 // FLOATING POINT INSTRUCTION FORMATS
528 // opcode - operation code.
530 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
531 // fd - dst reg, only used on 3 regs instr.
532 // fmt - double or single precision.
533 // funct - combined with opcode field give us an operation code.
535 //===----------------------------------------------------------------------===//
537 //===----------------------------------------------------------------------===//
538 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
539 //===----------------------------------------------------------------------===//
541 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
542 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
550 let Inst{25-21} = base;
551 let Inst{20-16} = ft;
552 let Inst{15-0} = imm16;
555 class ADDS_FM<bits<6> funct, bits<5> fmt> {
562 let Inst{31-26} = 0x11;
563 let Inst{25-21} = fmt;
564 let Inst{20-16} = ft;
565 let Inst{15-11} = fs;
567 let Inst{5-0} = funct;
570 class ABSS_FM<bits<6> funct, bits<5> fmt> {
576 let Inst{31-26} = 0x11;
577 let Inst{25-21} = fmt;
579 let Inst{15-11} = fs;
581 let Inst{5-0} = funct;
584 class MFC1_FM<bits<5> funct> {
590 let Inst{31-26} = 0x11;
591 let Inst{25-21} = funct;
592 let Inst{20-16} = rt;
593 let Inst{15-11} = fs;
597 class LW_FM<bits<6> op> : StdArch {
603 let Inst{31-26} = op;
604 let Inst{25-21} = addr{20-16};
605 let Inst{20-16} = rt;
606 let Inst{15-0} = addr{15-0};
609 class MADDS_FM<bits<3> funct, bits<3> fmt> {
617 let Inst{31-26} = 0x13;
618 let Inst{25-21} = fr;
619 let Inst{20-16} = ft;
620 let Inst{15-11} = fs;
622 let Inst{5-3} = funct;
626 class LWXC1_FM<bits<6> funct> {
633 let Inst{31-26} = 0x13;
634 let Inst{25-21} = base;
635 let Inst{20-16} = index;
638 let Inst{5-0} = funct;
641 class SWXC1_FM<bits<6> funct> {
648 let Inst{31-26} = 0x13;
649 let Inst{25-21} = base;
650 let Inst{20-16} = index;
651 let Inst{15-11} = fs;
653 let Inst{5-0} = funct;
656 class BC1F_FM<bit nd, bit tf> {
662 let Inst{31-26} = 0x11;
663 let Inst{25-21} = 0x8;
664 let Inst{20-18} = fcc;
667 let Inst{15-0} = offset;
670 class CEQS_FM<bits<5> fmt> {
677 let Inst{31-26} = 0x11;
678 let Inst{25-21} = fmt;
679 let Inst{20-16} = ft;
680 let Inst{15-11} = fs;
681 let Inst{10-8} = 0; // cc
683 let Inst{3-0} = cond;
686 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
690 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
697 let Inst{31-26} = 0x11;
698 let Inst{25-21} = fmt;
699 let Inst{20-16} = rt;
700 let Inst{15-11} = fs;
702 let Inst{5-0} = funct;
705 class CMov_F_I_FM<bit tf> {
713 let Inst{25-21} = rs;
714 let Inst{20-18} = fcc;
717 let Inst{15-11} = rd;
722 class CMov_F_F_FM<bits<5> fmt, bit tf> {
729 let Inst{31-26} = 0x11;
730 let Inst{25-21} = fmt;
731 let Inst{20-18} = fcc;
734 let Inst{15-11} = fs;
736 let Inst{5-0} = 0x11;