1 //===- MipsInstrFormats.td - Mips Instruction Formats ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Generic Mips Format
25 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
26 InstrItinClass itin>: Instruction
30 let Namespace = "Mips";
34 // Top 5 bits are the 'opcode' field
35 let Inst{31-26} = opcode;
37 dag OutOperandList = outs;
38 dag InOperandList = ins;
40 let AsmString = asmstr;
41 let Pattern = pattern;
45 // Mips Pseudo Instructions Format
46 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
47 MipsInst<outs, ins, asmstr, pattern, IIPseudo> {
51 //===----------------------------------------------------------------------===//
52 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
53 //===----------------------------------------------------------------------===//
55 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
56 list<dag> pattern, InstrItinClass itin>:
57 MipsInst<outs, ins, asmstr, pattern, itin>
71 let Inst{10-6} = shamt;
72 let Inst{5-0} = funct;
75 //===----------------------------------------------------------------------===//
76 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
77 //===----------------------------------------------------------------------===//
79 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
80 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
90 let Inst{15-0} = imm16;
93 //===----------------------------------------------------------------------===//
94 // Format J instruction class in Mips : <|opcode|address|>
95 //===----------------------------------------------------------------------===//
97 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
98 InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
104 let Inst{25-0} = addr;
107 //===----------------------------------------------------------------------===//
109 // FLOATING POINT INSTRUCTION FORMATS
111 // opcode - operation code.
113 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
114 // fd - dst reg, only used on 3 regs instr.
115 // fmt - double or single precision.
116 // funct - combined with opcode field give us an operation code.
118 //===----------------------------------------------------------------------===//
120 //===----------------------------------------------------------------------===//
121 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
122 //===----------------------------------------------------------------------===//
124 class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
125 string asmstr, list<dag> pattern> :
126 MipsInst<outs, ins, asmstr, pattern, NoItinerary>
138 let Inst{25-21} = fmt;
139 let Inst{20-16} = ft;
140 let Inst{15-11} = fs;
142 let Inst{5-0} = funct;
145 //===----------------------------------------------------------------------===//
146 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
147 //===----------------------------------------------------------------------===//
149 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
150 MipsInst<outs, ins, asmstr, pattern, NoItinerary>
158 let Inst{25-21} = base;
159 let Inst{20-16} = ft;
160 let Inst{15-0} = imm16;
163 //===----------------------------------------------------------------------===//
164 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
165 //===----------------------------------------------------------------------===//
167 class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
168 MipsInst<outs, ins, asmstr, pattern, NoItinerary>
178 let Inst{25-21} = fmt;
179 let Inst{20-16} = ft;
180 let Inst{15-11} = fs;
182 let Inst{5-4} = 0b11;
187 class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
189 MipsInst<outs, ins, asmstr, pattern, NoItinerary>
199 let Inst{25-21} = rs;
203 let Inst{15-11} = rd;
208 class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
210 MipsInst<outs, ins, asmstr, pattern, NoItinerary>
222 let Inst{25-21} = fmt;
226 let Inst{15-11} = fs;
231 // FP unary instructions without patterns.
232 class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
233 RegisterClass DstRC, RegisterClass SrcRC> :
234 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
235 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
239 // FP unary instructions with patterns.
240 class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
241 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
242 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
243 !strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
244 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {