1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
39 // Generic Mips Format
40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41 InstrItinClass itin, Format f>: Instruction
46 let Namespace = "Mips";
52 // Top 6 bits are the 'opcode' field
53 let Inst{31-26} = Opcode;
55 let OutOperandList = outs;
56 let InOperandList = ins;
58 let AsmString = asmstr;
59 let Pattern = pattern;
63 // Attributes specific to Mips instructions...
65 bits<4> FormBits = Form.Value;
67 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68 let TSFlags{3-0} = FormBits;
70 let DecoderNamespace = "Mips";
72 field bits<32> SoftFail = 0;
75 // Mips32/64 Instruction Format
76 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77 InstrItinClass itin, Format f>:
78 MipsInst<outs, ins, asmstr, pattern, itin, f> {
79 let Predicates = [HasStdEnc];
82 // Mips Pseudo Instructions Format
83 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
84 MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
85 let isCodeGenOnly = 1;
89 // Mips32/64 Pseudo Instruction Format
90 class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>:
91 MipsPseudo<outs, ins, asmstr, pattern> {
92 let Predicates = [HasStdEnc];
95 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
96 // These are aliases that require C++ handling to convert to the target
97 // instruction, while InstAliases can be handled directly by tblgen.
98 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
99 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
103 //===----------------------------------------------------------------------===//
104 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
105 //===----------------------------------------------------------------------===//
107 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
108 list<dag> pattern, InstrItinClass itin>:
109 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
120 let Inst{25-21} = rs;
121 let Inst{20-16} = rt;
122 let Inst{15-11} = rd;
123 let Inst{10-6} = shamt;
124 let Inst{5-0} = funct;
127 //===----------------------------------------------------------------------===//
128 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
129 //===----------------------------------------------------------------------===//
131 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
132 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
140 let Inst{25-21} = rs;
141 let Inst{20-16} = rt;
142 let Inst{15-0} = imm16;
145 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
146 list<dag> pattern, InstrItinClass itin>:
147 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
155 let Inst{25-21} = rs;
156 let Inst{20-16} = rt;
157 let Inst{15-0} = imm16;
160 //===----------------------------------------------------------------------===//
161 // Format J instruction class in Mips : <|opcode|address|>
162 //===----------------------------------------------------------------------===//
164 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
165 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
171 let Inst{25-0} = addr;
174 //===----------------------------------------------------------------------===//
175 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
176 //===----------------------------------------------------------------------===//
177 class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
178 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
188 let Inst{25-21} = mfmt;
189 let Inst{20-16} = rt;
190 let Inst{15-11} = rd;
195 class ADD_FM<bits<6> op, bits<6> funct> {
202 let Inst{31-26} = op;
203 let Inst{25-21} = rs;
204 let Inst{20-16} = rt;
205 let Inst{15-11} = rd;
207 let Inst{5-0} = funct;
210 class ADDI_FM<bits<6> op> {
217 let Inst{31-26} = op;
218 let Inst{25-21} = rs;
219 let Inst{20-16} = rt;
220 let Inst{15-0} = imm16;
223 class SRA_FM<bits<6> funct, bit rotate> {
232 let Inst{21} = rotate;
233 let Inst{20-16} = rt;
234 let Inst{15-11} = rd;
235 let Inst{10-6} = shamt;
236 let Inst{5-0} = funct;
239 class SRLV_FM<bits<6> funct, bit rotate> {
247 let Inst{25-21} = rs;
248 let Inst{20-16} = rt;
249 let Inst{15-11} = rd;
251 let Inst{6} = rotate;
252 let Inst{5-0} = funct;
255 //===----------------------------------------------------------------------===//
257 // FLOATING POINT INSTRUCTION FORMATS
259 // opcode - operation code.
261 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
262 // fd - dst reg, only used on 3 regs instr.
263 // fmt - double or single precision.
264 // funct - combined with opcode field give us an operation code.
266 //===----------------------------------------------------------------------===//
268 //===----------------------------------------------------------------------===//
269 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
270 //===----------------------------------------------------------------------===//
272 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
273 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
281 let Inst{25-21} = base;
282 let Inst{20-16} = ft;
283 let Inst{15-0} = imm16;
286 class ADDS_FM<bits<6> funct, bits<5> fmt> {
293 let Inst{31-26} = 0x11;
294 let Inst{25-21} = fmt;
295 let Inst{20-16} = ft;
296 let Inst{15-11} = fs;
298 let Inst{5-0} = funct;
301 class ABSS_FM<bits<6> funct, bits<5> fmt> {
307 let Inst{31-26} = 0x11;
308 let Inst{25-21} = fmt;
310 let Inst{15-11} = fs;
312 let Inst{5-0} = funct;
315 class MFC1_FM<bits<5> funct> {
321 let Inst{31-26} = 0x11;
322 let Inst{25-21} = funct;
323 let Inst{20-16} = rt;
324 let Inst{15-11} = fs;
328 class LW_FM<bits<6> op> {
334 let Inst{31-26} = op;
335 let Inst{25-21} = addr{20-16};
336 let Inst{20-16} = rt;
337 let Inst{15-0} = addr{15-0};
340 class MADDS_FM<bits<3> funct, bits<3> fmt> {
348 let Inst{31-26} = 0x13;
349 let Inst{25-21} = fr;
350 let Inst{20-16} = ft;
351 let Inst{15-11} = fs;
353 let Inst{5-3} = funct;
357 class LWXC1_FM<bits<6> funct> {
364 let Inst{31-26} = 0x13;
365 let Inst{25-21} = base;
366 let Inst{20-16} = index;
369 let Inst{5-0} = funct;
372 class SWXC1_FM<bits<6> funct> {
379 let Inst{31-26} = 0x13;
380 let Inst{25-21} = base;
381 let Inst{20-16} = index;
382 let Inst{15-11} = fs;
384 let Inst{5-0} = funct;
387 class BC1F_FM<bit nd, bit tf> {
392 let Inst{31-26} = 0x11;
393 let Inst{25-21} = 0x8;
394 let Inst{20-18} = 0; // cc
397 let Inst{15-0} = offset;
400 class CEQS_FM<bits<5> fmt> {
407 let Inst{31-26} = 0x11;
408 let Inst{25-21} = fmt;
409 let Inst{20-16} = ft;
410 let Inst{15-11} = fs;
411 let Inst{10-8} = 0; // cc
413 let Inst{3-0} = cond;
416 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
423 let Inst{31-26} = 0x11;
424 let Inst{25-21} = fmt;
425 let Inst{20-16} = rt;
426 let Inst{15-11} = fs;
428 let Inst{5-0} = funct;
431 class CMov_F_I_FM<bit tf> {
438 let Inst{25-21} = rs;
439 let Inst{20-18} = 0; // cc
442 let Inst{15-11} = rd;
447 class CMov_F_F_FM<bits<5> fmt, bit tf> {
453 let Inst{31-26} = 0x11;
454 let Inst{25-21} = fmt;
455 let Inst{20-18} = 0; // cc
458 let Inst{15-11} = fs;
460 let Inst{5-0} = 0x11;