1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
24 #define GET_INSTRINFO_CTOR
25 #include "MipsGenInstrInfo.inc"
29 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
30 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
31 TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
32 RI(*TM.getSubtargetImpl(), *this) {}
35 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
39 static bool isZeroImm(const MachineOperand &op) {
40 return op.isImm() && op.getImm() == 0;
43 /// isLoadFromStackSlot - If the specified machine instruction is a direct
44 /// load from a stack slot, return the virtual or physical register number of
45 /// the destination along with the FrameIndex of the loaded stack slot. If
46 /// not, return 0. This predicate must return 0 if the instruction has
47 /// any side effects other than loading from the stack slot.
48 unsigned MipsInstrInfo::
49 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
51 unsigned Opc = MI->getOpcode();
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
56 (Opc == Mips::LDC164_P8)) {
57 if ((MI->getOperand(1).isFI()) && // is a stack slot
58 (MI->getOperand(2).isImm()) && // the imm is zero
59 (isZeroImm(MI->getOperand(2)))) {
60 FrameIndex = MI->getOperand(1).getIndex();
61 return MI->getOperand(0).getReg();
68 /// isStoreToStackSlot - If the specified machine instruction is a direct
69 /// store to a stack slot, return the virtual or physical register number of
70 /// the source reg along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than storing to the stack slot.
73 unsigned MipsInstrInfo::
74 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
76 unsigned Opc = MI->getOpcode();
78 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
79 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
80 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
81 (Opc == Mips::SDC164_P8)) {
82 if ((MI->getOperand(1).isFI()) && // is a stack slot
83 (MI->getOperand(2).isImm()) && // the imm is zero
84 (isZeroImm(MI->getOperand(2)))) {
85 FrameIndex = MI->getOperand(1).getIndex();
86 return MI->getOperand(0).getReg();
92 /// insertNoop - If data hazard condition is found insert the target nop
95 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
98 BuildMI(MBB, MI, DL, get(Mips::NOP));
102 copyPhysReg(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator I, DebugLoc DL,
104 unsigned DestReg, unsigned SrcReg,
105 bool KillSrc) const {
106 unsigned Opc = 0, ZeroReg = 0;
108 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
109 if (Mips::CPURegsRegClass.contains(SrcReg))
110 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
111 else if (Mips::CCRRegClass.contains(SrcReg))
113 else if (Mips::FGR32RegClass.contains(SrcReg))
115 else if (SrcReg == Mips::HI)
116 Opc = Mips::MFHI, SrcReg = 0;
117 else if (SrcReg == Mips::LO)
118 Opc = Mips::MFLO, SrcReg = 0;
120 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
121 if (Mips::CCRRegClass.contains(DestReg))
123 else if (Mips::FGR32RegClass.contains(DestReg))
125 else if (DestReg == Mips::HI)
126 Opc = Mips::MTHI, DestReg = 0;
127 else if (DestReg == Mips::LO)
128 Opc = Mips::MTLO, DestReg = 0;
130 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
132 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
133 Opc = Mips::FMOV_D32;
134 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
135 Opc = Mips::FMOV_D64;
136 else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
137 Opc = Mips::MOVCCRToCCR;
138 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
139 if (Mips::CPU64RegsRegClass.contains(SrcReg))
140 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
141 else if (SrcReg == Mips::HI64)
142 Opc = Mips::MFHI64, SrcReg = 0;
143 else if (SrcReg == Mips::LO64)
144 Opc = Mips::MFLO64, SrcReg = 0;
145 else if (Mips::FGR64RegClass.contains(SrcReg))
148 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
149 if (DestReg == Mips::HI64)
150 Opc = Mips::MTHI64, DestReg = 0;
151 else if (DestReg == Mips::LO64)
152 Opc = Mips::MTLO64, DestReg = 0;
153 else if (Mips::FGR64RegClass.contains(DestReg))
157 assert(Opc && "Cannot copy registers");
159 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
162 MIB.addReg(DestReg, RegState::Define);
168 MIB.addReg(SrcReg, getKillRegState(KillSrc));
172 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
173 unsigned SrcReg, bool isKill, int FI,
174 const TargetRegisterClass *RC,
175 const TargetRegisterInfo *TRI) const {
177 if (I != MBB.end()) DL = I->getDebugLoc();
180 if (RC == Mips::CPURegsRegisterClass)
181 Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
182 else if (RC == Mips::CPU64RegsRegisterClass)
183 Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
184 else if (RC == Mips::FGR32RegisterClass)
185 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
186 else if (RC == Mips::AFGR64RegisterClass)
188 else if (RC == Mips::FGR64RegisterClass)
189 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
191 assert(Opc && "Register class not handled!");
192 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
193 .addFrameIndex(FI).addImm(0);
197 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
198 unsigned DestReg, int FI,
199 const TargetRegisterClass *RC,
200 const TargetRegisterInfo *TRI) const
203 if (I != MBB.end()) DL = I->getDebugLoc();
206 if (RC == Mips::CPURegsRegisterClass)
207 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
208 else if (RC == Mips::CPU64RegsRegisterClass)
209 Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
210 else if (RC == Mips::FGR32RegisterClass)
211 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
212 else if (RC == Mips::AFGR64RegisterClass)
214 else if (RC == Mips::FGR64RegisterClass)
215 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
217 assert(Opc && "Register class not handled!");
218 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0);
222 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
223 uint64_t Offset, const MDNode *MDPtr,
225 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
226 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
230 //===----------------------------------------------------------------------===//
232 //===----------------------------------------------------------------------===//
234 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
235 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
236 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
237 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
238 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
239 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B) ?
243 /// GetOppositeBranchOpc - Return the inverse of the specified
244 /// opcode, e.g. turning BEQ to BNE.
245 unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
248 default: llvm_unreachable("Illegal opcode!");
249 case Mips::BEQ : return Mips::BNE;
250 case Mips::BNE : return Mips::BEQ;
251 case Mips::BGTZ : return Mips::BLEZ;
252 case Mips::BGEZ : return Mips::BLTZ;
253 case Mips::BLTZ : return Mips::BGEZ;
254 case Mips::BLEZ : return Mips::BGTZ;
255 case Mips::BEQ64 : return Mips::BNE64;
256 case Mips::BNE64 : return Mips::BEQ64;
257 case Mips::BGTZ64 : return Mips::BLEZ64;
258 case Mips::BGEZ64 : return Mips::BLTZ64;
259 case Mips::BLTZ64 : return Mips::BGEZ64;
260 case Mips::BLEZ64 : return Mips::BGTZ64;
261 case Mips::BC1T : return Mips::BC1F;
262 case Mips::BC1F : return Mips::BC1T;
266 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
267 MachineBasicBlock *&BB,
268 SmallVectorImpl<MachineOperand>& Cond) {
269 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
270 int NumOp = Inst->getNumExplicitOperands();
272 // for both int and fp branches, the last explicit operand is the
274 BB = Inst->getOperand(NumOp-1).getMBB();
275 Cond.push_back(MachineOperand::CreateImm(Opc));
277 for (int i=0; i<NumOp-1; i++)
278 Cond.push_back(Inst->getOperand(i));
281 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
282 MachineBasicBlock *&TBB,
283 MachineBasicBlock *&FBB,
284 SmallVectorImpl<MachineOperand> &Cond,
285 bool AllowModify) const
287 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
289 // Skip all the debug instructions.
290 while (I != REnd && I->isDebugValue())
293 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
294 // If this block ends with no branches (it just falls through to its succ)
295 // just return false, leaving TBB/FBB null.
300 MachineInstr *LastInst = &*I;
301 unsigned LastOpc = LastInst->getOpcode();
303 // Not an analyzable branch (must be an indirect jump).
304 if (!GetAnalyzableBrOpc(LastOpc))
307 // Get the second to last instruction in the block.
308 unsigned SecondLastOpc = 0;
309 MachineInstr *SecondLastInst = NULL;
312 SecondLastInst = &*I;
313 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
315 // Not an analyzable branch (must be an indirect jump).
316 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
320 // If there is only one terminator instruction, process it.
321 if (!SecondLastOpc) {
322 // Unconditional branch
323 if (LastOpc == Mips::B) {
324 TBB = LastInst->getOperand(0).getMBB();
328 // Conditional branch
329 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
333 // If we reached here, there are two branches.
334 // If there are three terminators, we don't know what sort of block this is.
335 if (++I != REnd && isUnpredicatedTerminator(&*I))
338 // If second to last instruction is an unconditional branch,
339 // analyze it and remove the last instruction.
340 if (SecondLastOpc == Mips::B) {
341 // Return if the last instruction cannot be removed.
345 TBB = SecondLastInst->getOperand(0).getMBB();
346 LastInst->eraseFromParent();
350 // Conditional branch followed by an unconditional branch.
351 // The last one must be unconditional.
352 if (LastOpc != Mips::B)
355 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
356 FBB = LastInst->getOperand(0).getMBB();
361 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
362 MachineBasicBlock *TBB, DebugLoc DL,
363 const SmallVectorImpl<MachineOperand>& Cond)
365 unsigned Opc = Cond[0].getImm();
366 const MCInstrDesc &MCID = get(Opc);
367 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
369 for (unsigned i = 1; i < Cond.size(); ++i)
370 MIB.addReg(Cond[i].getReg());
375 unsigned MipsInstrInfo::
376 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
377 MachineBasicBlock *FBB,
378 const SmallVectorImpl<MachineOperand> &Cond,
380 // Shouldn't be a fall through.
381 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
383 // # of condition operands:
384 // Unconditional branches: 0
385 // Floating point branches: 1 (opc)
386 // Int BranchZero: 2 (opc, reg)
387 // Int Branch: 3 (opc, reg0, reg1)
388 assert((Cond.size() <= 3) &&
389 "# of Mips branch conditions must be <= 3!");
391 // Two-way Conditional branch.
393 BuildCondBr(MBB, TBB, DL, Cond);
394 BuildMI(&MBB, DL, get(Mips::B)).addMBB(FBB);
399 // Unconditional branch.
401 BuildMI(&MBB, DL, get(Mips::B)).addMBB(TBB);
402 else // Conditional branch.
403 BuildCondBr(MBB, TBB, DL, Cond);
407 unsigned MipsInstrInfo::
408 RemoveBranch(MachineBasicBlock &MBB) const
410 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
411 MachineBasicBlock::reverse_iterator FirstBr;
414 // Skip all the debug instructions.
415 while (I != REnd && I->isDebugValue())
420 // Up to 2 branches are removed.
421 // Note that indirect branches are not removed.
422 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
423 if (!GetAnalyzableBrOpc(I->getOpcode()))
426 MBB.erase(I.base(), FirstBr.base());
431 /// ReverseBranchCondition - Return the inverse opcode of the
432 /// specified Branch instruction.
434 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
436 assert( (Cond.size() && Cond.size() <= 3) &&
437 "Invalid Mips branch condition!");
438 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
442 /// getGlobalBaseReg - Return a virtual register initialized with the
443 /// the global base register value. Output instructions required to
444 /// initialize the register in the function entry block, if necessary.
446 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
447 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
448 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
449 if (GlobalBaseReg != 0)
450 return GlobalBaseReg;
452 // Insert the set of GlobalBaseReg into the first MBB of the function
453 MachineBasicBlock &FirstMBB = MF->front();
454 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
455 MachineRegisterInfo &RegInfo = MF->getRegInfo();
456 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
458 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
459 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
460 GlobalBaseReg).addReg(Mips::GP);
461 RegInfo.addLiveIn(Mips::GP);
463 MipsFI->setGlobalBaseReg(GlobalBaseReg);
464 return GlobalBaseReg;