1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MipsGenInstrInfo.inc"
25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
39 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
41 // addu $dst, $src, $zero || addu $dst, $zero, $src
42 // or $dst, $src, $zero || or $dst, $zero, $src
43 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44 if (MI.getOperand(1).getReg() == Mips::ZERO) {
45 DstReg = MI.getOperand(0).getReg();
46 SrcReg = MI.getOperand(2).getReg();
48 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
58 if (MI.getOpcode() == Mips::FMOV_S32 ||
59 MI.getOpcode() == Mips::FMOV_D32 ||
60 MI.getOpcode() == Mips::MFC1 ||
61 MI.getOpcode() == Mips::MTC1 ||
62 MI.getOpcode() == Mips::MOVCCRToCCR) {
63 DstReg = MI.getOperand(0).getReg();
64 SrcReg = MI.getOperand(1).getReg();
68 // addiu $dst, $src, 0
69 if (MI.getOpcode() == Mips::ADDiu) {
70 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71 DstReg = MI.getOperand(0).getReg();
72 SrcReg = MI.getOperand(1).getReg();
80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
81 /// load from a stack slot, return the virtual or physical register number of
82 /// the destination along with the FrameIndex of the loaded stack slot. If
83 /// not, return 0. This predicate must return 0 if the instruction has
84 /// any side effects other than loading from the stack slot.
85 unsigned MipsInstrInfo::
86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
88 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89 (MI->getOpcode() == Mips::LDC1)) {
90 if ((MI->getOperand(2).isFI()) && // is a stack slot
91 (MI->getOperand(1).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(1)))) {
93 FrameIndex = MI->getOperand(2).getIndex();
94 return MI->getOperand(0).getReg();
101 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// store to a stack slot, return the virtual or physical register number of
103 /// the source reg along with the FrameIndex of the loaded stack slot. If
104 /// not, return 0. This predicate must return 0 if the instruction has
105 /// any side effects other than storing to the stack slot.
106 unsigned MipsInstrInfo::
107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
109 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110 (MI->getOpcode() == Mips::SDC1)) {
111 if ((MI->getOperand(2).isFI()) && // is a stack slot
112 (MI->getOperand(1).isImm()) && // the imm is zero
113 (isZeroImm(MI->getOperand(1)))) {
114 FrameIndex = MI->getOperand(2).getIndex();
115 return MI->getOperand(0).getReg();
121 /// insertNoop - If data hazard condition is found insert the target nop
124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
126 DebugLoc DL = DebugLoc::getUnknownLoc();
127 if (MI != MBB.end()) DL = MI->getDebugLoc();
128 BuildMI(MBB, MI, DL, get(Mips::NOP));
132 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
133 unsigned DestReg, unsigned SrcReg,
134 const TargetRegisterClass *DestRC,
135 const TargetRegisterClass *SrcRC) const {
136 DebugLoc DL = DebugLoc::getUnknownLoc();
138 if (I != MBB.end()) DL = I->getDebugLoc();
140 if (DestRC != SrcRC) {
142 // Copy to/from FCR31 condition register
143 if ((DestRC == Mips::CPURegsRegisterClass) &&
144 (SrcRC == Mips::CCRRegisterClass))
145 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
146 else if ((DestRC == Mips::CCRRegisterClass) &&
147 (SrcRC == Mips::CPURegsRegisterClass))
148 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
150 // Moves between coprocessors and cpu
151 else if ((DestRC == Mips::CPURegsRegisterClass) &&
152 (SrcRC == Mips::FGR32RegisterClass))
153 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
154 else if ((DestRC == Mips::FGR32RegisterClass) &&
155 (SrcRC == Mips::CPURegsRegisterClass))
156 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
158 // Move from/to Hi/Lo registers
159 else if ((DestRC == Mips::HILORegisterClass) &&
160 (SrcRC == Mips::CPURegsRegisterClass)) {
161 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
162 BuildMI(MBB, I, DL, get(Opc), DestReg);
163 } else if ((SrcRC == Mips::HILORegisterClass) &&
164 (DestRC == Mips::CPURegsRegisterClass)) {
165 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
166 BuildMI(MBB, I, DL, get(Opc), DestReg);
168 // Can't copy this register
174 if (DestRC == Mips::CPURegsRegisterClass)
175 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
177 else if (DestRC == Mips::FGR32RegisterClass)
178 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
179 else if (DestRC == Mips::AFGR64RegisterClass)
180 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
181 else if (DestRC == Mips::CCRRegisterClass)
182 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
184 // Can't copy this register
191 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
192 unsigned SrcReg, bool isKill, int FI,
193 const TargetRegisterClass *RC) const {
194 DebugLoc DL = DebugLoc::getUnknownLoc();
195 if (I != MBB.end()) DL = I->getDebugLoc();
197 if (RC == Mips::CPURegsRegisterClass)
198 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
199 .addImm(0).addFrameIndex(FI);
200 else if (RC == Mips::FGR32RegisterClass)
201 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
202 .addImm(0).addFrameIndex(FI);
203 else if (RC == Mips::AFGR64RegisterClass) {
204 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
205 BuildMI(MBB, I, DL, get(Mips::SDC1))
206 .addReg(SrcReg, getKillRegState(isKill))
207 .addImm(0).addFrameIndex(FI);
209 const TargetRegisterInfo *TRI =
210 MBB.getParent()->getTarget().getRegisterInfo();
211 const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
212 BuildMI(MBB, I, DL, get(Mips::SWC1))
213 .addReg(SubSet[0], getKillRegState(isKill))
214 .addImm(0).addFrameIndex(FI);
215 BuildMI(MBB, I, DL, get(Mips::SWC1))
216 .addReg(SubSet[1], getKillRegState(isKill))
217 .addImm(4).addFrameIndex(FI);
220 llvm_unreachable("Register class not handled!");
224 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
225 unsigned DestReg, int FI,
226 const TargetRegisterClass *RC) const
228 DebugLoc DL = DebugLoc::getUnknownLoc();
229 if (I != MBB.end()) DL = I->getDebugLoc();
231 if (RC == Mips::CPURegsRegisterClass)
232 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
233 else if (RC == Mips::FGR32RegisterClass)
234 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
235 else if (RC == Mips::AFGR64RegisterClass) {
236 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
237 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
239 const TargetRegisterInfo *TRI =
240 MBB.getParent()->getTarget().getRegisterInfo();
241 const unsigned *SubSet = TRI->getSubRegisters(DestReg);
242 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
243 .addImm(0).addFrameIndex(FI);
244 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
245 .addImm(4).addFrameIndex(FI);
248 llvm_unreachable("Register class not handled!");
251 MachineInstr *MipsInstrInfo::
252 foldMemoryOperandImpl(MachineFunction &MF,
254 const SmallVectorImpl<unsigned> &Ops, int FI) const
256 if (Ops.size() != 1) return NULL;
258 MachineInstr *NewMI = NULL;
260 switch (MI->getOpcode()) {
262 if ((MI->getOperand(0).isReg()) &&
263 (MI->getOperand(1).isReg()) &&
264 (MI->getOperand(1).getReg() == Mips::ZERO) &&
265 (MI->getOperand(2).isReg())) {
266 if (Ops[0] == 0) { // COPY -> STORE
267 unsigned SrcReg = MI->getOperand(2).getReg();
268 bool isKill = MI->getOperand(2).isKill();
269 bool isUndef = MI->getOperand(2).isUndef();
270 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
271 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
272 .addImm(0).addFrameIndex(FI);
273 } else { // COPY -> LOAD
274 unsigned DstReg = MI->getOperand(0).getReg();
275 bool isDead = MI->getOperand(0).isDead();
276 bool isUndef = MI->getOperand(0).isUndef();
277 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
278 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
279 getUndefRegState(isUndef))
280 .addImm(0).addFrameIndex(FI);
286 if ((MI->getOperand(0).isReg()) &&
287 (MI->getOperand(1).isReg())) {
288 const TargetRegisterClass
289 *RC = RI.getRegClass(MI->getOperand(0).getReg());
290 unsigned StoreOpc, LoadOpc;
291 bool IsMips1 = TM.getSubtarget<MipsSubtarget>().isMips1();
293 if (RC == Mips::FGR32RegisterClass) {
294 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
296 assert(RC == Mips::AFGR64RegisterClass);
297 // Mips1 doesn't have ldc/sdc instructions.
299 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
302 if (Ops[0] == 0) { // COPY -> STORE
303 unsigned SrcReg = MI->getOperand(1).getReg();
304 bool isKill = MI->getOperand(1).isKill();
305 bool isUndef = MI->getOperand(2).isUndef();
306 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
307 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
308 .addImm(0).addFrameIndex(FI) ;
309 } else { // COPY -> LOAD
310 unsigned DstReg = MI->getOperand(0).getReg();
311 bool isDead = MI->getOperand(0).isDead();
312 bool isUndef = MI->getOperand(0).isUndef();
313 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
314 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
315 getUndefRegState(isUndef))
316 .addImm(0).addFrameIndex(FI);
325 //===----------------------------------------------------------------------===//
327 //===----------------------------------------------------------------------===//
329 /// GetCondFromBranchOpc - Return the Mips CC that matches
330 /// the correspondent Branch instruction opcode.
331 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
334 default: return Mips::COND_INVALID;
335 case Mips::BEQ : return Mips::COND_E;
336 case Mips::BNE : return Mips::COND_NE;
337 case Mips::BGTZ : return Mips::COND_GZ;
338 case Mips::BGEZ : return Mips::COND_GEZ;
339 case Mips::BLTZ : return Mips::COND_LZ;
340 case Mips::BLEZ : return Mips::COND_LEZ;
342 // We dont do fp branch analysis yet!
344 case Mips::BC1F : return Mips::COND_INVALID;
348 /// GetCondBranchFromCond - Return the Branch instruction
349 /// opcode that matches the cc.
350 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
353 default: llvm_unreachable("Illegal condition code!");
354 case Mips::COND_E : return Mips::BEQ;
355 case Mips::COND_NE : return Mips::BNE;
356 case Mips::COND_GZ : return Mips::BGTZ;
357 case Mips::COND_GEZ : return Mips::BGEZ;
358 case Mips::COND_LZ : return Mips::BLTZ;
359 case Mips::COND_LEZ : return Mips::BLEZ;
364 case Mips::FCOND_UEQ:
365 case Mips::FCOND_OLT:
366 case Mips::FCOND_ULT:
367 case Mips::FCOND_OLE:
368 case Mips::FCOND_ULE:
370 case Mips::FCOND_NGLE:
371 case Mips::FCOND_SEQ:
372 case Mips::FCOND_NGL:
374 case Mips::FCOND_NGE:
376 case Mips::FCOND_NGT: return Mips::BC1T;
380 case Mips::FCOND_NEQ:
381 case Mips::FCOND_OGL:
382 case Mips::FCOND_UGE:
383 case Mips::FCOND_OGE:
384 case Mips::FCOND_UGT:
385 case Mips::FCOND_OGT:
387 case Mips::FCOND_GLE:
388 case Mips::FCOND_SNE:
390 case Mips::FCOND_NLT:
392 case Mips::FCOND_NLE:
393 case Mips::FCOND_GT: return Mips::BC1F;
397 /// GetOppositeBranchCondition - Return the inverse of the specified
398 /// condition, e.g. turning COND_E to COND_NE.
399 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
402 default: llvm_unreachable("Illegal condition code!");
403 case Mips::COND_E : return Mips::COND_NE;
404 case Mips::COND_NE : return Mips::COND_E;
405 case Mips::COND_GZ : return Mips::COND_LEZ;
406 case Mips::COND_GEZ : return Mips::COND_LZ;
407 case Mips::COND_LZ : return Mips::COND_GEZ;
408 case Mips::COND_LEZ : return Mips::COND_GZ;
409 case Mips::FCOND_F : return Mips::FCOND_T;
410 case Mips::FCOND_UN : return Mips::FCOND_OR;
411 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
412 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
413 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
414 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
415 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
416 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
417 case Mips::FCOND_SF: return Mips::FCOND_ST;
418 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
419 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
420 case Mips::FCOND_NGL: return Mips::FCOND_GL;
421 case Mips::FCOND_LT: return Mips::FCOND_NLT;
422 case Mips::FCOND_NGE: return Mips::FCOND_GE;
423 case Mips::FCOND_LE: return Mips::FCOND_NLE;
424 case Mips::FCOND_NGT: return Mips::FCOND_GT;
428 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
429 MachineBasicBlock *&TBB,
430 MachineBasicBlock *&FBB,
431 SmallVectorImpl<MachineOperand> &Cond,
432 bool AllowModify) const
434 // If the block has no terminators, it just falls into the block after it.
435 MachineBasicBlock::iterator I = MBB.end();
436 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
439 // Get the last instruction in the block.
440 MachineInstr *LastInst = I;
442 // If there is only one terminator instruction, process it.
443 unsigned LastOpc = LastInst->getOpcode();
444 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
445 if (!LastInst->getDesc().isBranch())
448 // Unconditional branch
449 if (LastOpc == Mips::J) {
450 TBB = LastInst->getOperand(0).getMBB();
454 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
455 if (BranchCode == Mips::COND_INVALID)
456 return true; // Can't handle indirect branch.
458 // Conditional branch
459 // Block ends with fall-through condbranch.
460 if (LastOpc != Mips::COND_INVALID) {
461 int LastNumOp = LastInst->getNumOperands();
463 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
464 Cond.push_back(MachineOperand::CreateImm(BranchCode));
466 for (int i=0; i<LastNumOp-1; i++) {
467 Cond.push_back(LastInst->getOperand(i));
474 // Get the instruction before it if it is a terminator.
475 MachineInstr *SecondLastInst = I;
477 // If there are three terminators, we don't know what sort of block this is.
478 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
481 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
482 unsigned SecondLastOpc = SecondLastInst->getOpcode();
483 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
485 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
486 int SecondNumOp = SecondLastInst->getNumOperands();
488 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
489 Cond.push_back(MachineOperand::CreateImm(BranchCode));
491 for (int i=0; i<SecondNumOp-1; i++) {
492 Cond.push_back(SecondLastInst->getOperand(i));
495 FBB = LastInst->getOperand(0).getMBB();
499 // If the block ends with two unconditional branches, handle it. The last
500 // one is not executed, so remove it.
501 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
502 TBB = SecondLastInst->getOperand(0).getMBB();
505 I->eraseFromParent();
509 // Otherwise, can't handle this.
513 unsigned MipsInstrInfo::
514 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
515 MachineBasicBlock *FBB,
516 const SmallVectorImpl<MachineOperand> &Cond) const {
517 // FIXME this should probably have a DebugLoc argument
518 DebugLoc dl = DebugLoc::getUnknownLoc();
519 // Shouldn't be a fall through.
520 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
521 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
522 "Mips branch conditions can have two|three components!");
524 if (FBB == 0) { // One way branch.
526 // Unconditional branch?
527 BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
529 // Conditional branch.
530 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
531 const TargetInstrDesc &TID = get(Opc);
533 if (TID.getNumOperands() == 3)
534 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
535 .addReg(Cond[2].getReg())
538 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
545 // Two-way Conditional branch.
546 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
547 const TargetInstrDesc &TID = get(Opc);
549 if (TID.getNumOperands() == 3)
550 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
553 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
555 BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
559 unsigned MipsInstrInfo::
560 RemoveBranch(MachineBasicBlock &MBB) const
562 MachineBasicBlock::iterator I = MBB.end();
563 if (I == MBB.begin()) return 0;
565 if (I->getOpcode() != Mips::J &&
566 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
569 // Remove the branch.
570 I->eraseFromParent();
574 if (I == MBB.begin()) return 1;
576 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
579 // Remove the branch.
580 I->eraseFromParent();
584 /// ReverseBranchCondition - Return the inverse opcode of the
585 /// specified Branch instruction.
587 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
589 assert( (Cond.size() == 3 || Cond.size() == 2) &&
590 "Invalid Mips branch condition!");
591 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
595 /// getGlobalBaseReg - Return a virtual register initialized with the
596 /// the global base register value. Output instructions required to
597 /// initialize the register in the function entry block, if necessary.
599 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
600 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
601 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
602 if (GlobalBaseReg != 0)
603 return GlobalBaseReg;
605 // Insert the set of GlobalBaseReg into the first MBB of the function
606 MachineBasicBlock &FirstMBB = MF->front();
607 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
608 MachineRegisterInfo &RegInfo = MF->getRegInfo();
609 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
611 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
612 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
613 Mips::CPURegsRegisterClass,
614 Mips::CPURegsRegisterClass);
615 assert(Ok && "Couldn't assign to global base register!");
616 Ok = Ok; // Silence warning when assertions are turned off.
617 RegInfo.addLiveIn(Mips::GP);
619 MipsFI->setGlobalBaseReg(GlobalBaseReg);
620 return GlobalBaseReg;