1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsInstrInfo.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "MipsGenInstrInfo.inc"
22 // TODO: Add the subtarget support on this constructor
23 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
24 : TargetInstrInfo(MipsInsts, array_lengthof(MipsInsts)),
27 static bool isZeroImm(const MachineOperand &op) {
28 return op.isImmediate() && op.getImmedValue() == 0;
31 /// Return true if the instruction is a register to register move and
32 /// leave the source and dest operands in the passed parameters.
34 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const
36 // addu $dst, $src, $zero || addu $dst, $zero, $src
37 // or $dst, $src, $zero || or $dst, $zero, $src
38 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR))
40 if (MI.getOperand(1).getReg() == Mips::ZERO) {
41 DstReg = MI.getOperand(0).getReg();
42 SrcReg = MI.getOperand(2).getReg();
44 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
45 DstReg = MI.getOperand(0).getReg();
46 SrcReg = MI.getOperand(1).getReg();
51 // addiu $dst, $src, 0
52 if (MI.getOpcode() == Mips::ADDiu)
54 if ((MI.getOperand(1).isRegister()) && (isZeroImm(MI.getOperand(2)))) {
55 DstReg = MI.getOperand(0).getReg();
56 SrcReg = MI.getOperand(1).getReg();
63 /// isLoadFromStackSlot - If the specified machine instruction is a direct
64 /// load from a stack slot, return the virtual or physical register number of
65 /// the destination along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than loading from the stack slot.
68 unsigned MipsInstrInfo::
69 isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
71 if (MI->getOpcode() == Mips::LW)
73 if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
74 (MI->getOperand(1).isImmediate()) && // the imm is zero
75 (isZeroImm(MI->getOperand(1))))
77 FrameIndex = MI->getOperand(2).getFrameIndex();
78 return MI->getOperand(0).getReg();
85 /// isStoreToStackSlot - If the specified machine instruction is a direct
86 /// store to a stack slot, return the virtual or physical register number of
87 /// the source reg along with the FrameIndex of the loaded stack slot. If
88 /// not, return 0. This predicate must return 0 if the instruction has
89 /// any side effects other than storing to the stack slot.
90 unsigned MipsInstrInfo::
91 isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
93 if (MI->getOpcode() == Mips::SW) {
94 if ((MI->getOperand(0).isFrameIndex()) && // is a stack slot
95 (MI->getOperand(1).isImmediate()) && // the imm is zero
96 (isZeroImm(MI->getOperand(1))))
98 FrameIndex = MI->getOperand(0).getFrameIndex();
99 return MI->getOperand(2).getReg();
105 /// insertNoop - If data hazard condition is found insert the target nop
108 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
110 BuildMI(MBB, MI, get(Mips::NOP));
113 //===----------------------------------------------------------------------===//
115 //===----------------------------------------------------------------------===//
117 /// GetCondFromBranchOpc - Return the Mips CC that matches
118 /// the correspondent Branch instruction opcode.
119 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
122 default: return Mips::COND_INVALID;
123 case Mips::BEQ : return Mips::COND_E;
124 case Mips::BNE : return Mips::COND_NE;
125 case Mips::BGTZ : return Mips::COND_GZ;
126 case Mips::BGEZ : return Mips::COND_GEZ;
127 case Mips::BLTZ : return Mips::COND_LZ;
128 case Mips::BLEZ : return Mips::COND_LEZ;
132 /// GetCondBranchFromCond - Return the Branch instruction
133 /// opcode that matches the cc.
134 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
137 default: assert(0 && "Illegal condition code!");
138 case Mips::COND_E : return Mips::BEQ;
139 case Mips::COND_NE : return Mips::BNE;
140 case Mips::COND_GZ : return Mips::BGTZ;
141 case Mips::COND_GEZ : return Mips::BGEZ;
142 case Mips::COND_LZ : return Mips::BLTZ;
143 case Mips::COND_LEZ : return Mips::BLEZ;
147 /// GetOppositeBranchCondition - Return the inverse of the specified
148 /// condition, e.g. turning COND_E to COND_NE.
149 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
152 default: assert(0 && "Illegal condition code!");
153 case Mips::COND_E : return Mips::COND_NE;
154 case Mips::COND_NE : return Mips::COND_E;
155 case Mips::COND_GZ : return Mips::COND_LEZ;
156 case Mips::COND_GEZ : return Mips::COND_LZ;
157 case Mips::COND_LZ : return Mips::COND_GEZ;
158 case Mips::COND_LEZ : return Mips::COND_GZ;
162 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
163 MachineBasicBlock *&TBB,
164 MachineBasicBlock *&FBB,
165 std::vector<MachineOperand> &Cond) const
167 // If the block has no terminators, it just falls into the block after it.
168 MachineBasicBlock::iterator I = MBB.end();
169 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
172 // Get the last instruction in the block.
173 MachineInstr *LastInst = I;
175 // If there is only one terminator instruction, process it.
176 unsigned LastOpc = LastInst->getOpcode();
177 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
178 if (!isBranch(LastInst->getOpcode()))
181 // Unconditional branch
182 if (LastOpc == Mips::J) {
183 TBB = LastInst->getOperand(0).getMachineBasicBlock();
187 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
188 if (BranchCode == Mips::COND_INVALID)
189 return true; // Can't handle indirect branch.
191 // Conditional branch
192 // Block ends with fall-through condbranch.
193 if (LastOpc != Mips::COND_INVALID) {
194 int LastNumOp = LastInst->getNumOperands();
196 TBB = LastInst->getOperand(LastNumOp-1).getMachineBasicBlock();
197 Cond.push_back(MachineOperand::CreateImm(BranchCode));
199 for (int i=0; i<LastNumOp-1; i++) {
200 Cond.push_back(LastInst->getOperand(i));
207 // Get the instruction before it if it is a terminator.
208 MachineInstr *SecondLastInst = I;
210 // If there are three terminators, we don't know what sort of block this is.
211 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
214 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
215 unsigned SecondLastOpc = SecondLastInst->getOpcode();
216 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
218 if (SecondLastOpc != Mips::COND_INVALID && LastOpc == Mips::J) {
219 int SecondNumOp = SecondLastInst->getNumOperands();
221 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMachineBasicBlock();
222 Cond.push_back(MachineOperand::CreateImm(BranchCode));
224 for (int i=0; i<SecondNumOp-1; i++) {
225 Cond.push_back(SecondLastInst->getOperand(i));
228 FBB = LastInst->getOperand(0).getMachineBasicBlock();
232 // If the block ends with two unconditional branches, handle it. The last
233 // one is not executed, so remove it.
234 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
235 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
237 I->eraseFromParent();
241 // Otherwise, can't handle this.
245 unsigned MipsInstrInfo::
246 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
247 MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond)
250 // Shouldn't be a fall through.
251 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
252 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
253 "Mips branch conditions can have two|three components!");
255 if (FBB == 0) { // One way branch.
257 // Unconditional branch?
258 BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
260 // Conditional branch.
261 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
262 const TargetInstrDescriptor &TID = get(Opc);
264 if (TID.numOperands == 3)
265 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
266 .addReg(Cond[2].getReg())
269 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
276 // Two-way Conditional branch.
277 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
278 const TargetInstrDescriptor &TID = get(Opc);
280 if (TID.numOperands == 3)
281 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
282 .addReg(Cond[2].getReg())
285 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
288 BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
292 unsigned MipsInstrInfo::
293 RemoveBranch(MachineBasicBlock &MBB) const
295 MachineBasicBlock::iterator I = MBB.end();
296 if (I == MBB.begin()) return 0;
298 if (I->getOpcode() != Mips::J &&
299 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
302 // Remove the branch.
303 I->eraseFromParent();
307 if (I == MBB.begin()) return 1;
309 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
312 // Remove the branch.
313 I->eraseFromParent();
317 /// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
318 /// fall-through into its successor block.
320 BlockHasNoFallThrough(MachineBasicBlock &MBB) const
322 if (MBB.empty()) return false;
324 switch (MBB.back().getOpcode()) {
325 case Mips::RET: // Return.
326 case Mips::JR: // Indirect branch.
327 case Mips::J: // Uncond branch.
329 default: return false;
333 /// ReverseBranchCondition - Return the inverse opcode of the
334 /// specified Branch instruction.
336 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const
338 assert( (Cond.size() == 3 || Cond.size() == 2) &&
339 "Invalid Mips branch condition!");
340 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));