1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MipsGenInstrInfo.inc"
25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
39 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
41 // addu $dst, $src, $zero || addu $dst, $zero, $src
42 // or $dst, $src, $zero || or $dst, $zero, $src
43 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44 if (MI.getOperand(1).getReg() == Mips::ZERO) {
45 DstReg = MI.getOperand(0).getReg();
46 SrcReg = MI.getOperand(2).getReg();
48 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
58 if (MI.getOpcode() == Mips::FMOV_S32 ||
59 MI.getOpcode() == Mips::FMOV_D32 ||
60 MI.getOpcode() == Mips::MFC1 ||
61 MI.getOpcode() == Mips::MTC1 ||
62 MI.getOpcode() == Mips::MOVCCRToCCR) {
63 DstReg = MI.getOperand(0).getReg();
64 SrcReg = MI.getOperand(1).getReg();
68 // addiu $dst, $src, 0
69 if (MI.getOpcode() == Mips::ADDiu) {
70 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71 DstReg = MI.getOperand(0).getReg();
72 SrcReg = MI.getOperand(1).getReg();
80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
81 /// load from a stack slot, return the virtual or physical register number of
82 /// the destination along with the FrameIndex of the loaded stack slot. If
83 /// not, return 0. This predicate must return 0 if the instruction has
84 /// any side effects other than loading from the stack slot.
85 unsigned MipsInstrInfo::
86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
88 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89 (MI->getOpcode() == Mips::LDC1)) {
90 if ((MI->getOperand(2).isFI()) && // is a stack slot
91 (MI->getOperand(1).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(1)))) {
93 FrameIndex = MI->getOperand(2).getIndex();
94 return MI->getOperand(0).getReg();
101 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// store to a stack slot, return the virtual or physical register number of
103 /// the source reg along with the FrameIndex of the loaded stack slot. If
104 /// not, return 0. This predicate must return 0 if the instruction has
105 /// any side effects other than storing to the stack slot.
106 unsigned MipsInstrInfo::
107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
109 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110 (MI->getOpcode() == Mips::SDC1)) {
111 if ((MI->getOperand(2).isFI()) && // is a stack slot
112 (MI->getOperand(1).isImm()) && // the imm is zero
113 (isZeroImm(MI->getOperand(1)))) {
114 FrameIndex = MI->getOperand(2).getIndex();
115 return MI->getOperand(0).getReg();
121 /// insertNoop - If data hazard condition is found insert the target nop
124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
126 DebugLoc DL = DebugLoc::getUnknownLoc();
127 if (MI != MBB.end()) DL = MI->getDebugLoc();
128 BuildMI(MBB, MI, DL, get(Mips::NOP));
132 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
133 unsigned DestReg, unsigned SrcReg,
134 const TargetRegisterClass *DestRC,
135 const TargetRegisterClass *SrcRC) const {
136 DebugLoc DL = DebugLoc::getUnknownLoc();
137 const MachineFunction *MF = MBB.getParent();
138 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
140 if (I != MBB.end()) DL = I->getDebugLoc();
142 if (DestRC != SrcRC) {
144 // Copy to/from FCR31 condition register
145 if ((DestRC == Mips::CPURegsRegisterClass) &&
146 (SrcRC == Mips::CCRRegisterClass))
147 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
148 else if ((DestRC == Mips::CCRRegisterClass) &&
149 (SrcRC == Mips::CPURegsRegisterClass))
150 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
152 // Moves between coprocessors and cpu
153 else if ((DestRC == Mips::CPURegsRegisterClass) &&
154 (SrcRC == Mips::FGR32RegisterClass))
155 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
156 else if ((DestRC == Mips::FGR32RegisterClass) &&
157 (SrcRC == Mips::CPURegsRegisterClass))
158 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
159 else if ((DestRC == Mips::AFGR64RegisterClass) &&
160 (SrcRC == Mips::CPURegsRegisterClass) &&
161 (SrcReg == Mips::ZERO)) {
162 const unsigned *AliasSet = TRI->getAliasSet(DestReg);
163 BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[0]).addReg(SrcReg);
164 BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[1]).addReg(SrcReg);
167 // Move from/to Hi/Lo registers
168 else if ((DestRC == Mips::HILORegisterClass) &&
169 (SrcRC == Mips::CPURegsRegisterClass)) {
170 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
171 BuildMI(MBB, I, DL, get(Opc), DestReg);
172 } else if ((SrcRC == Mips::HILORegisterClass) &&
173 (DestRC == Mips::CPURegsRegisterClass)) {
174 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
175 BuildMI(MBB, I, DL, get(Opc), DestReg);
177 // Can't copy this register
183 if (DestRC == Mips::CPURegsRegisterClass)
184 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
186 else if (DestRC == Mips::FGR32RegisterClass)
187 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
188 else if (DestRC == Mips::AFGR64RegisterClass)
189 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
190 else if (DestRC == Mips::CCRRegisterClass)
191 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
193 // Can't copy this register
200 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
201 unsigned SrcReg, bool isKill, int FI,
202 const TargetRegisterClass *RC) const {
203 DebugLoc DL = DebugLoc::getUnknownLoc();
204 if (I != MBB.end()) DL = I->getDebugLoc();
206 if (RC == Mips::CPURegsRegisterClass)
207 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
208 .addImm(0).addFrameIndex(FI);
209 else if (RC == Mips::FGR32RegisterClass)
210 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
211 .addImm(0).addFrameIndex(FI);
212 else if (RC == Mips::AFGR64RegisterClass) {
213 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
214 BuildMI(MBB, I, DL, get(Mips::SDC1))
215 .addReg(SrcReg, getKillRegState(isKill))
216 .addImm(0).addFrameIndex(FI);
218 const TargetRegisterInfo *TRI =
219 MBB.getParent()->getTarget().getRegisterInfo();
220 const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
221 BuildMI(MBB, I, DL, get(Mips::SWC1))
222 .addReg(SubSet[0], getKillRegState(isKill))
223 .addImm(0).addFrameIndex(FI);
224 BuildMI(MBB, I, DL, get(Mips::SWC1))
225 .addReg(SubSet[1], getKillRegState(isKill))
226 .addImm(4).addFrameIndex(FI);
229 llvm_unreachable("Register class not handled!");
233 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
234 unsigned DestReg, int FI,
235 const TargetRegisterClass *RC) const
237 DebugLoc DL = DebugLoc::getUnknownLoc();
238 if (I != MBB.end()) DL = I->getDebugLoc();
240 if (RC == Mips::CPURegsRegisterClass)
241 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
242 else if (RC == Mips::FGR32RegisterClass)
243 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
244 else if (RC == Mips::AFGR64RegisterClass) {
245 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
246 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
248 const TargetRegisterInfo *TRI =
249 MBB.getParent()->getTarget().getRegisterInfo();
250 const unsigned *SubSet = TRI->getSubRegisters(DestReg);
251 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
252 .addImm(0).addFrameIndex(FI);
253 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
254 .addImm(4).addFrameIndex(FI);
257 llvm_unreachable("Register class not handled!");
260 MachineInstr *MipsInstrInfo::
261 foldMemoryOperandImpl(MachineFunction &MF,
263 const SmallVectorImpl<unsigned> &Ops, int FI) const
265 if (Ops.size() != 1) return NULL;
267 MachineInstr *NewMI = NULL;
269 switch (MI->getOpcode()) {
271 if ((MI->getOperand(0).isReg()) &&
272 (MI->getOperand(1).isReg()) &&
273 (MI->getOperand(1).getReg() == Mips::ZERO) &&
274 (MI->getOperand(2).isReg())) {
275 if (Ops[0] == 0) { // COPY -> STORE
276 unsigned SrcReg = MI->getOperand(2).getReg();
277 bool isKill = MI->getOperand(2).isKill();
278 bool isUndef = MI->getOperand(2).isUndef();
279 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
280 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
281 .addImm(0).addFrameIndex(FI);
282 } else { // COPY -> LOAD
283 unsigned DstReg = MI->getOperand(0).getReg();
284 bool isDead = MI->getOperand(0).isDead();
285 bool isUndef = MI->getOperand(0).isUndef();
286 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
287 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
288 getUndefRegState(isUndef))
289 .addImm(0).addFrameIndex(FI);
295 if ((MI->getOperand(0).isReg()) &&
296 (MI->getOperand(1).isReg())) {
297 const TargetRegisterClass
298 *RC = RI.getRegClass(MI->getOperand(0).getReg());
299 unsigned StoreOpc, LoadOpc;
300 bool IsMips1 = TM.getSubtarget<MipsSubtarget>().isMips1();
302 if (RC == Mips::FGR32RegisterClass) {
303 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
305 assert(RC == Mips::AFGR64RegisterClass);
306 // Mips1 doesn't have ldc/sdc instructions.
308 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
311 if (Ops[0] == 0) { // COPY -> STORE
312 unsigned SrcReg = MI->getOperand(1).getReg();
313 bool isKill = MI->getOperand(1).isKill();
314 bool isUndef = MI->getOperand(2).isUndef();
315 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
316 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
317 .addImm(0).addFrameIndex(FI) ;
318 } else { // COPY -> LOAD
319 unsigned DstReg = MI->getOperand(0).getReg();
320 bool isDead = MI->getOperand(0).isDead();
321 bool isUndef = MI->getOperand(0).isUndef();
322 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
323 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
324 getUndefRegState(isUndef))
325 .addImm(0).addFrameIndex(FI);
334 //===----------------------------------------------------------------------===//
336 //===----------------------------------------------------------------------===//
338 /// GetCondFromBranchOpc - Return the Mips CC that matches
339 /// the correspondent Branch instruction opcode.
340 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
343 default: return Mips::COND_INVALID;
344 case Mips::BEQ : return Mips::COND_E;
345 case Mips::BNE : return Mips::COND_NE;
346 case Mips::BGTZ : return Mips::COND_GZ;
347 case Mips::BGEZ : return Mips::COND_GEZ;
348 case Mips::BLTZ : return Mips::COND_LZ;
349 case Mips::BLEZ : return Mips::COND_LEZ;
351 // We dont do fp branch analysis yet!
353 case Mips::BC1F : return Mips::COND_INVALID;
357 /// GetCondBranchFromCond - Return the Branch instruction
358 /// opcode that matches the cc.
359 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
362 default: llvm_unreachable("Illegal condition code!");
363 case Mips::COND_E : return Mips::BEQ;
364 case Mips::COND_NE : return Mips::BNE;
365 case Mips::COND_GZ : return Mips::BGTZ;
366 case Mips::COND_GEZ : return Mips::BGEZ;
367 case Mips::COND_LZ : return Mips::BLTZ;
368 case Mips::COND_LEZ : return Mips::BLEZ;
373 case Mips::FCOND_UEQ:
374 case Mips::FCOND_OLT:
375 case Mips::FCOND_ULT:
376 case Mips::FCOND_OLE:
377 case Mips::FCOND_ULE:
379 case Mips::FCOND_NGLE:
380 case Mips::FCOND_SEQ:
381 case Mips::FCOND_NGL:
383 case Mips::FCOND_NGE:
385 case Mips::FCOND_NGT: return Mips::BC1T;
389 case Mips::FCOND_NEQ:
390 case Mips::FCOND_OGL:
391 case Mips::FCOND_UGE:
392 case Mips::FCOND_OGE:
393 case Mips::FCOND_UGT:
394 case Mips::FCOND_OGT:
396 case Mips::FCOND_GLE:
397 case Mips::FCOND_SNE:
399 case Mips::FCOND_NLT:
401 case Mips::FCOND_NLE:
402 case Mips::FCOND_GT: return Mips::BC1F;
406 /// GetOppositeBranchCondition - Return the inverse of the specified
407 /// condition, e.g. turning COND_E to COND_NE.
408 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
411 default: llvm_unreachable("Illegal condition code!");
412 case Mips::COND_E : return Mips::COND_NE;
413 case Mips::COND_NE : return Mips::COND_E;
414 case Mips::COND_GZ : return Mips::COND_LEZ;
415 case Mips::COND_GEZ : return Mips::COND_LZ;
416 case Mips::COND_LZ : return Mips::COND_GEZ;
417 case Mips::COND_LEZ : return Mips::COND_GZ;
418 case Mips::FCOND_F : return Mips::FCOND_T;
419 case Mips::FCOND_UN : return Mips::FCOND_OR;
420 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
421 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
422 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
423 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
424 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
425 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
426 case Mips::FCOND_SF: return Mips::FCOND_ST;
427 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
428 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
429 case Mips::FCOND_NGL: return Mips::FCOND_GL;
430 case Mips::FCOND_LT: return Mips::FCOND_NLT;
431 case Mips::FCOND_NGE: return Mips::FCOND_GE;
432 case Mips::FCOND_LE: return Mips::FCOND_NLE;
433 case Mips::FCOND_NGT: return Mips::FCOND_GT;
437 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
438 MachineBasicBlock *&TBB,
439 MachineBasicBlock *&FBB,
440 SmallVectorImpl<MachineOperand> &Cond,
441 bool AllowModify) const
443 // If the block has no terminators, it just falls into the block after it.
444 MachineBasicBlock::iterator I = MBB.end();
445 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
448 // Get the last instruction in the block.
449 MachineInstr *LastInst = I;
451 // If there is only one terminator instruction, process it.
452 unsigned LastOpc = LastInst->getOpcode();
453 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
454 if (!LastInst->getDesc().isBranch())
457 // Unconditional branch
458 if (LastOpc == Mips::J) {
459 TBB = LastInst->getOperand(0).getMBB();
463 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
464 if (BranchCode == Mips::COND_INVALID)
465 return true; // Can't handle indirect branch.
467 // Conditional branch
468 // Block ends with fall-through condbranch.
469 if (LastOpc != Mips::COND_INVALID) {
470 int LastNumOp = LastInst->getNumOperands();
472 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
473 Cond.push_back(MachineOperand::CreateImm(BranchCode));
475 for (int i=0; i<LastNumOp-1; i++) {
476 Cond.push_back(LastInst->getOperand(i));
483 // Get the instruction before it if it is a terminator.
484 MachineInstr *SecondLastInst = I;
486 // If there are three terminators, we don't know what sort of block this is.
487 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
490 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
491 unsigned SecondLastOpc = SecondLastInst->getOpcode();
492 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
494 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
495 int SecondNumOp = SecondLastInst->getNumOperands();
497 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
498 Cond.push_back(MachineOperand::CreateImm(BranchCode));
500 for (int i=0; i<SecondNumOp-1; i++) {
501 Cond.push_back(SecondLastInst->getOperand(i));
504 FBB = LastInst->getOperand(0).getMBB();
508 // If the block ends with two unconditional branches, handle it. The last
509 // one is not executed, so remove it.
510 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
511 TBB = SecondLastInst->getOperand(0).getMBB();
514 I->eraseFromParent();
518 // Otherwise, can't handle this.
522 unsigned MipsInstrInfo::
523 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
524 MachineBasicBlock *FBB,
525 const SmallVectorImpl<MachineOperand> &Cond) const {
526 // FIXME this should probably have a DebugLoc argument
527 DebugLoc dl = DebugLoc::getUnknownLoc();
528 // Shouldn't be a fall through.
529 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
530 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
531 "Mips branch conditions can have two|three components!");
533 if (FBB == 0) { // One way branch.
535 // Unconditional branch?
536 BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
538 // Conditional branch.
539 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
540 const TargetInstrDesc &TID = get(Opc);
542 if (TID.getNumOperands() == 3)
543 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
544 .addReg(Cond[2].getReg())
547 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
554 // Two-way Conditional branch.
555 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
556 const TargetInstrDesc &TID = get(Opc);
558 if (TID.getNumOperands() == 3)
559 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
562 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
564 BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
568 unsigned MipsInstrInfo::
569 RemoveBranch(MachineBasicBlock &MBB) const
571 MachineBasicBlock::iterator I = MBB.end();
572 if (I == MBB.begin()) return 0;
574 if (I->getOpcode() != Mips::J &&
575 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
578 // Remove the branch.
579 I->eraseFromParent();
583 if (I == MBB.begin()) return 1;
585 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
588 // Remove the branch.
589 I->eraseFromParent();
593 /// ReverseBranchCondition - Return the inverse opcode of the
594 /// specified Branch instruction.
596 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
598 assert( (Cond.size() == 3 || Cond.size() == 2) &&
599 "Invalid Mips branch condition!");
600 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
604 /// getGlobalBaseReg - Return a virtual register initialized with the
605 /// the global base register value. Output instructions required to
606 /// initialize the register in the function entry block, if necessary.
608 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
609 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
610 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
611 if (GlobalBaseReg != 0)
612 return GlobalBaseReg;
614 // Insert the set of GlobalBaseReg into the first MBB of the function
615 MachineBasicBlock &FirstMBB = MF->front();
616 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
617 MachineRegisterInfo &RegInfo = MF->getRegInfo();
618 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
620 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
621 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
622 Mips::CPURegsRegisterClass,
623 Mips::CPURegsRegisterClass);
624 assert(Ok && "Couldn't assign to global base register!");
625 Ok = Ok; // Silence warning when assertions are turned off.
626 RegInfo.addLiveIn(Mips::GP);
628 MipsFI->setGlobalBaseReg(GlobalBaseReg);
629 return GlobalBaseReg;