1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "MipsGenInstrInfo.inc"
22 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
23 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
24 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
26 static bool isZeroImm(const MachineOperand &op) {
27 return op.isImmediate() && op.getImm() == 0;
30 /// Return true if the instruction is a register to register move and
31 /// leave the source and dest operands in the passed parameters.
33 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const
35 // addu $dst, $src, $zero || addu $dst, $zero, $src
36 // or $dst, $src, $zero || or $dst, $zero, $src
37 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
38 if (MI.getOperand(1).getReg() == Mips::ZERO) {
39 DstReg = MI.getOperand(0).getReg();
40 SrcReg = MI.getOperand(2).getReg();
42 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
43 DstReg = MI.getOperand(0).getReg();
44 SrcReg = MI.getOperand(1).getReg();
52 if (MI.getOpcode() == Mips::FMOV_SO32 || MI.getOpcode() == Mips::FMOV_AS32 ||
53 MI.getOpcode() == Mips::FMOV_D32 || MI.getOpcode() == Mips::MFC1A ||
54 MI.getOpcode() == Mips::MFC1 || MI.getOpcode() == Mips::MTC1A ||
55 MI.getOpcode() == Mips::MTC1 ) {
56 DstReg = MI.getOperand(0).getReg();
57 SrcReg = MI.getOperand(1).getReg();
61 // addiu $dst, $src, 0
62 if (MI.getOpcode() == Mips::ADDiu) {
63 if ((MI.getOperand(1).isRegister()) && (isZeroImm(MI.getOperand(2)))) {
64 DstReg = MI.getOperand(0).getReg();
65 SrcReg = MI.getOperand(1).getReg();
72 /// isLoadFromStackSlot - If the specified machine instruction is a direct
73 /// load from a stack slot, return the virtual or physical register number of
74 /// the destination along with the FrameIndex of the loaded stack slot. If
75 /// not, return 0. This predicate must return 0 if the instruction has
76 /// any side effects other than loading from the stack slot.
77 unsigned MipsInstrInfo::
78 isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
80 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
81 (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
82 if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
83 (MI->getOperand(1).isImmediate()) && // the imm is zero
84 (isZeroImm(MI->getOperand(1)))) {
85 FrameIndex = MI->getOperand(2).getIndex();
86 return MI->getOperand(0).getReg();
93 /// isStoreToStackSlot - If the specified machine instruction is a direct
94 /// store to a stack slot, return the virtual or physical register number of
95 /// the source reg along with the FrameIndex of the loaded stack slot. If
96 /// not, return 0. This predicate must return 0 if the instruction has
97 /// any side effects other than storing to the stack slot.
98 unsigned MipsInstrInfo::
99 isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
101 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
102 (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
103 if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
104 (MI->getOperand(1).isImmediate()) && // the imm is zero
105 (isZeroImm(MI->getOperand(1)))) {
106 FrameIndex = MI->getOperand(2).getIndex();
107 return MI->getOperand(0).getReg();
113 /// insertNoop - If data hazard condition is found insert the target nop
116 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
118 BuildMI(MBB, MI, get(Mips::NOP));
122 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
123 unsigned DestReg, unsigned SrcReg,
124 const TargetRegisterClass *DestRC,
125 const TargetRegisterClass *SrcRC) const {
126 if (DestRC != SrcRC) {
127 if ((DestRC == Mips::CPURegsRegisterClass) &&
128 (SrcRC == Mips::FGR32RegisterClass))
129 BuildMI(MBB, I, get(Mips::MFC1), DestReg).addReg(SrcReg);
130 else if ((DestRC == Mips::CPURegsRegisterClass) &&
131 (SrcRC == Mips::AFGR32RegisterClass))
132 BuildMI(MBB, I, get(Mips::MFC1A), DestReg).addReg(SrcReg);
133 else if ((DestRC == Mips::FGR32RegisterClass) &&
134 (SrcRC == Mips::CPURegsRegisterClass))
135 BuildMI(MBB, I, get(Mips::MTC1), DestReg).addReg(SrcReg);
136 else if ((DestRC == Mips::AFGR32RegisterClass) &&
137 (SrcRC == Mips::CPURegsRegisterClass))
138 BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
139 else if ((DestRC == Mips::AFGR32RegisterClass) &&
140 (SrcRC == Mips::CPURegsRegisterClass))
141 BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
142 else if ((SrcRC == Mips::CCRRegisterClass) &&
143 (SrcReg == Mips::FCR31))
144 return true; // This register is used implicitly, no copy needed.
145 else if ((DestRC == Mips::CCRRegisterClass) &&
146 (DestReg == Mips::FCR31))
147 return true; // This register is used implicitly, no copy needed.
148 else if ((DestRC == Mips::HILORegisterClass) &&
149 (SrcRC == Mips::CPURegsRegisterClass)) {
150 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
151 BuildMI(MBB, I, get(Opc), DestReg);
152 } else if ((SrcRC == Mips::HILORegisterClass) &&
153 (DestRC == Mips::CPURegsRegisterClass)) {
154 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
155 BuildMI(MBB, I, get(Opc), DestReg);
157 // DestRC != SrcRC, Can't copy this register
163 if (DestRC == Mips::CPURegsRegisterClass)
164 BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
166 else if (DestRC == Mips::FGR32RegisterClass)
167 BuildMI(MBB, I, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
168 else if (DestRC == Mips::AFGR32RegisterClass)
169 BuildMI(MBB, I, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
170 else if (DestRC == Mips::AFGR64RegisterClass)
171 BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
173 // Can't copy this register
180 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
181 unsigned SrcReg, bool isKill, int FI,
182 const TargetRegisterClass *RC) const
185 if (RC == Mips::CPURegsRegisterClass)
187 else if (RC == Mips::FGR32RegisterClass)
189 else if (RC == Mips::AFGR32RegisterClass)
191 else if (RC == Mips::AFGR64RegisterClass)
194 assert(0 && "Can't store this register to stack slot");
196 BuildMI(MBB, I, get(Opc)).addReg(SrcReg, false, false, isKill)
197 .addImm(0).addFrameIndex(FI);
200 void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
201 bool isKill, SmallVectorImpl<MachineOperand> &Addr,
202 const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
205 if (RC == Mips::CPURegsRegisterClass)
207 else if (RC == Mips::FGR32RegisterClass)
209 else if (RC == Mips::AFGR32RegisterClass)
211 else if (RC == Mips::AFGR64RegisterClass)
214 assert(0 && "Can't store this register");
216 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
217 .addReg(SrcReg, false, false, isKill);
218 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
219 MachineOperand &MO = Addr[i];
221 MIB.addReg(MO.getReg());
222 else if (MO.isImmediate())
223 MIB.addImm(MO.getImm());
225 MIB.addFrameIndex(MO.getIndex());
227 NewMIs.push_back(MIB);
232 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
233 unsigned DestReg, int FI,
234 const TargetRegisterClass *RC) const
237 if (RC == Mips::CPURegsRegisterClass)
239 else if (RC == Mips::FGR32RegisterClass)
241 else if (RC == Mips::AFGR32RegisterClass)
243 else if (RC == Mips::AFGR64RegisterClass)
246 assert(0 && "Can't load this register from stack slot");
248 BuildMI(MBB, I, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
251 void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
252 SmallVectorImpl<MachineOperand> &Addr,
253 const TargetRegisterClass *RC,
254 SmallVectorImpl<MachineInstr*> &NewMIs) const {
256 if (RC == Mips::CPURegsRegisterClass)
258 else if (RC == Mips::FGR32RegisterClass)
260 else if (RC == Mips::AFGR32RegisterClass)
262 else if (RC == Mips::AFGR64RegisterClass)
265 assert(0 && "Can't load this register");
267 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
268 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
269 MachineOperand &MO = Addr[i];
271 MIB.addReg(MO.getReg());
272 else if (MO.isImmediate())
273 MIB.addImm(MO.getImm());
275 MIB.addFrameIndex(MO.getIndex());
277 NewMIs.push_back(MIB);
281 MachineInstr *MipsInstrInfo::
282 foldMemoryOperand(MachineFunction &MF,
284 SmallVectorImpl<unsigned> &Ops, int FI) const
286 if (Ops.size() != 1) return NULL;
288 MachineInstr *NewMI = NULL;
290 switch (MI->getOpcode()) {
292 if ((MI->getOperand(0).isRegister()) &&
293 (MI->getOperand(1).isRegister()) &&
294 (MI->getOperand(1).getReg() == Mips::ZERO) &&
295 (MI->getOperand(2).isRegister())) {
296 if (Ops[0] == 0) { // COPY -> STORE
297 unsigned SrcReg = MI->getOperand(2).getReg();
298 bool isKill = MI->getOperand(2).isKill();
299 NewMI = BuildMI(MF, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
300 .addImm(0).addFrameIndex(FI);
301 } else { // COPY -> LOAD
302 unsigned DstReg = MI->getOperand(0).getReg();
303 bool isDead = MI->getOperand(0).isDead();
304 NewMI = BuildMI(MF, get(Mips::LW))
305 .addReg(DstReg, true, false, false, isDead)
306 .addImm(0).addFrameIndex(FI);
310 case Mips::FMOV_SO32:
311 case Mips::FMOV_AS32:
313 if ((MI->getOperand(0).isRegister()) &&
314 (MI->getOperand(1).isRegister())) {
315 const TargetRegisterClass
316 *RC = RI.getRegClass(MI->getOperand(0).getReg());
317 unsigned StoreOpc, LoadOpc;
319 if (RC == Mips::FGR32RegisterClass) {
320 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
321 } else if (RC == Mips::AFGR32RegisterClass) {
322 LoadOpc = Mips::LWC1A; StoreOpc = Mips::SWC1A;
323 } else if (RC == Mips::AFGR64RegisterClass) {
324 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
326 assert(0 && "foldMemoryOperand register unknown");
328 if (Ops[0] == 0) { // COPY -> STORE
329 unsigned SrcReg = MI->getOperand(1).getReg();
330 bool isKill = MI->getOperand(1).isKill();
331 NewMI = BuildMI(MF, get(StoreOpc)).addReg(SrcReg, false, false, isKill)
332 .addImm(0).addFrameIndex(FI) ;
333 } else { // COPY -> LOAD
334 unsigned DstReg = MI->getOperand(0).getReg();
335 bool isDead = MI->getOperand(0).isDead();
336 NewMI = BuildMI(MF, get(LoadOpc))
337 .addReg(DstReg, true, false, false, isDead)
338 .addImm(0).addFrameIndex(FI);
347 //===----------------------------------------------------------------------===//
349 //===----------------------------------------------------------------------===//
351 /// GetCondFromBranchOpc - Return the Mips CC that matches
352 /// the correspondent Branch instruction opcode.
353 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
356 default: return Mips::COND_INVALID;
357 case Mips::BEQ : return Mips::COND_E;
358 case Mips::BNE : return Mips::COND_NE;
359 case Mips::BGTZ : return Mips::COND_GZ;
360 case Mips::BGEZ : return Mips::COND_GEZ;
361 case Mips::BLTZ : return Mips::COND_LZ;
362 case Mips::BLEZ : return Mips::COND_LEZ;
364 // We dont do fp branch analysis yet!
366 case Mips::BC1F : return Mips::COND_INVALID;
370 /// GetCondBranchFromCond - Return the Branch instruction
371 /// opcode that matches the cc.
372 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
375 default: assert(0 && "Illegal condition code!");
376 case Mips::COND_E : return Mips::BEQ;
377 case Mips::COND_NE : return Mips::BNE;
378 case Mips::COND_GZ : return Mips::BGTZ;
379 case Mips::COND_GEZ : return Mips::BGEZ;
380 case Mips::COND_LZ : return Mips::BLTZ;
381 case Mips::COND_LEZ : return Mips::BLEZ;
386 case Mips::FCOND_UEQ:
387 case Mips::FCOND_OLT:
388 case Mips::FCOND_ULT:
389 case Mips::FCOND_OLE:
390 case Mips::FCOND_ULE:
392 case Mips::FCOND_NGLE:
393 case Mips::FCOND_SEQ:
394 case Mips::FCOND_NGL:
396 case Mips::FCOND_NGE:
398 case Mips::FCOND_NGT: return Mips::BC1T;
402 case Mips::FCOND_NEQ:
403 case Mips::FCOND_OGL:
404 case Mips::FCOND_UGE:
405 case Mips::FCOND_OGE:
406 case Mips::FCOND_UGT:
407 case Mips::FCOND_OGT:
409 case Mips::FCOND_GLE:
410 case Mips::FCOND_SNE:
412 case Mips::FCOND_NLT:
414 case Mips::FCOND_NLE:
415 case Mips::FCOND_GT: return Mips::BC1F;
419 /// GetOppositeBranchCondition - Return the inverse of the specified
420 /// condition, e.g. turning COND_E to COND_NE.
421 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
424 default: assert(0 && "Illegal condition code!");
425 case Mips::COND_E : return Mips::COND_NE;
426 case Mips::COND_NE : return Mips::COND_E;
427 case Mips::COND_GZ : return Mips::COND_LEZ;
428 case Mips::COND_GEZ : return Mips::COND_LZ;
429 case Mips::COND_LZ : return Mips::COND_GEZ;
430 case Mips::COND_LEZ : return Mips::COND_GZ;
431 case Mips::FCOND_F : return Mips::FCOND_T;
432 case Mips::FCOND_UN : return Mips::FCOND_OR;
433 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
434 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
435 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
436 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
437 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
438 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
439 case Mips::FCOND_SF: return Mips::FCOND_ST;
440 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
441 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
442 case Mips::FCOND_NGL: return Mips::FCOND_GL;
443 case Mips::FCOND_LT: return Mips::FCOND_NLT;
444 case Mips::FCOND_NGE: return Mips::FCOND_GE;
445 case Mips::FCOND_LE: return Mips::FCOND_NLE;
446 case Mips::FCOND_NGT: return Mips::FCOND_GT;
450 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
451 MachineBasicBlock *&TBB,
452 MachineBasicBlock *&FBB,
453 SmallVectorImpl<MachineOperand> &Cond) const
455 // If the block has no terminators, it just falls into the block after it.
456 MachineBasicBlock::iterator I = MBB.end();
457 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
460 // Get the last instruction in the block.
461 MachineInstr *LastInst = I;
463 // If there is only one terminator instruction, process it.
464 unsigned LastOpc = LastInst->getOpcode();
465 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
466 if (!LastInst->getDesc().isBranch())
469 // Unconditional branch
470 if (LastOpc == Mips::J) {
471 TBB = LastInst->getOperand(0).getMBB();
475 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
476 if (BranchCode == Mips::COND_INVALID)
477 return true; // Can't handle indirect branch.
479 // Conditional branch
480 // Block ends with fall-through condbranch.
481 if (LastOpc != Mips::COND_INVALID) {
482 int LastNumOp = LastInst->getNumOperands();
484 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
485 Cond.push_back(MachineOperand::CreateImm(BranchCode));
487 for (int i=0; i<LastNumOp-1; i++) {
488 Cond.push_back(LastInst->getOperand(i));
495 // Get the instruction before it if it is a terminator.
496 MachineInstr *SecondLastInst = I;
498 // If there are three terminators, we don't know what sort of block this is.
499 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
502 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
503 unsigned SecondLastOpc = SecondLastInst->getOpcode();
504 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
506 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
507 int SecondNumOp = SecondLastInst->getNumOperands();
509 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
510 Cond.push_back(MachineOperand::CreateImm(BranchCode));
512 for (int i=0; i<SecondNumOp-1; i++) {
513 Cond.push_back(SecondLastInst->getOperand(i));
516 FBB = LastInst->getOperand(0).getMBB();
520 // If the block ends with two unconditional branches, handle it. The last
521 // one is not executed, so remove it.
522 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
523 TBB = SecondLastInst->getOperand(0).getMBB();
525 I->eraseFromParent();
529 // Otherwise, can't handle this.
533 unsigned MipsInstrInfo::
534 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
535 MachineBasicBlock *FBB,
536 const SmallVectorImpl<MachineOperand> &Cond) const {
537 // Shouldn't be a fall through.
538 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
539 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
540 "Mips branch conditions can have two|three components!");
542 if (FBB == 0) { // One way branch.
544 // Unconditional branch?
545 BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
547 // Conditional branch.
548 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
549 const TargetInstrDesc &TID = get(Opc);
551 if (TID.getNumOperands() == 3)
552 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
553 .addReg(Cond[2].getReg())
556 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
563 // Two-way Conditional branch.
564 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
565 const TargetInstrDesc &TID = get(Opc);
567 if (TID.getNumOperands() == 3)
568 BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
571 BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
573 BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
577 unsigned MipsInstrInfo::
578 RemoveBranch(MachineBasicBlock &MBB) const
580 MachineBasicBlock::iterator I = MBB.end();
581 if (I == MBB.begin()) return 0;
583 if (I->getOpcode() != Mips::J &&
584 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
587 // Remove the branch.
588 I->eraseFromParent();
592 if (I == MBB.begin()) return 1;
594 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
597 // Remove the branch.
598 I->eraseFromParent();
602 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
603 /// fall-through into its successor block.
605 BlockHasNoFallThrough(MachineBasicBlock &MBB) const
607 if (MBB.empty()) return false;
609 switch (MBB.back().getOpcode()) {
610 case Mips::RET: // Return.
611 case Mips::JR: // Indirect branch.
612 case Mips::J: // Uncond branch.
614 default: return false;
618 /// ReverseBranchCondition - Return the inverse opcode of the
619 /// specified Branch instruction.
621 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
623 assert( (Cond.size() == 3 || Cond.size() == 2) &&
624 "Invalid Mips branch condition!");
625 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));