1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MipsGenInstrInfo.inc"
25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
39 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
41 // addu $dst, $src, $zero || addu $dst, $zero, $src
42 // or $dst, $src, $zero || or $dst, $zero, $src
43 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44 if (MI.getOperand(1).getReg() == Mips::ZERO) {
45 DstReg = MI.getOperand(0).getReg();
46 SrcReg = MI.getOperand(2).getReg();
48 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
58 if (MI.getOpcode() == Mips::FMOV_S32 ||
59 MI.getOpcode() == Mips::FMOV_D32 ||
60 MI.getOpcode() == Mips::MFC1 ||
61 MI.getOpcode() == Mips::MTC1 ||
62 MI.getOpcode() == Mips::MOVCCRToCCR) {
63 DstReg = MI.getOperand(0).getReg();
64 SrcReg = MI.getOperand(1).getReg();
68 // addiu $dst, $src, 0
69 if (MI.getOpcode() == Mips::ADDiu) {
70 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71 DstReg = MI.getOperand(0).getReg();
72 SrcReg = MI.getOperand(1).getReg();
80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
81 /// load from a stack slot, return the virtual or physical register number of
82 /// the destination along with the FrameIndex of the loaded stack slot. If
83 /// not, return 0. This predicate must return 0 if the instruction has
84 /// any side effects other than loading from the stack slot.
85 unsigned MipsInstrInfo::
86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
88 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89 (MI->getOpcode() == Mips::LDC1)) {
90 if ((MI->getOperand(2).isFI()) && // is a stack slot
91 (MI->getOperand(1).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(1)))) {
93 FrameIndex = MI->getOperand(2).getIndex();
94 return MI->getOperand(0).getReg();
101 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// store to a stack slot, return the virtual or physical register number of
103 /// the source reg along with the FrameIndex of the loaded stack slot. If
104 /// not, return 0. This predicate must return 0 if the instruction has
105 /// any side effects other than storing to the stack slot.
106 unsigned MipsInstrInfo::
107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
109 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110 (MI->getOpcode() == Mips::SDC1)) {
111 if ((MI->getOperand(2).isFI()) && // is a stack slot
112 (MI->getOperand(1).isImm()) && // the imm is zero
113 (isZeroImm(MI->getOperand(1)))) {
114 FrameIndex = MI->getOperand(2).getIndex();
115 return MI->getOperand(0).getReg();
121 /// insertNoop - If data hazard condition is found insert the target nop
124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
127 BuildMI(MBB, MI, DL, get(Mips::NOP));
131 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
132 unsigned DestReg, unsigned SrcReg,
133 const TargetRegisterClass *DestRC,
134 const TargetRegisterClass *SrcRC) const {
137 if (I != MBB.end()) DL = I->getDebugLoc();
139 if (DestRC != SrcRC) {
141 // Copy to/from FCR31 condition register
142 if ((DestRC == Mips::CPURegsRegisterClass) &&
143 (SrcRC == Mips::CCRRegisterClass))
144 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
145 else if ((DestRC == Mips::CCRRegisterClass) &&
146 (SrcRC == Mips::CPURegsRegisterClass))
147 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
149 // Moves between coprocessors and cpu
150 else if ((DestRC == Mips::CPURegsRegisterClass) &&
151 (SrcRC == Mips::FGR32RegisterClass))
152 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
153 else if ((DestRC == Mips::FGR32RegisterClass) &&
154 (SrcRC == Mips::CPURegsRegisterClass))
155 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
157 // Move from/to Hi/Lo registers
158 else if ((DestRC == Mips::HILORegisterClass) &&
159 (SrcRC == Mips::CPURegsRegisterClass)) {
160 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
161 BuildMI(MBB, I, DL, get(Opc), DestReg);
162 } else if ((SrcRC == Mips::HILORegisterClass) &&
163 (DestRC == Mips::CPURegsRegisterClass)) {
164 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
165 BuildMI(MBB, I, DL, get(Opc), DestReg);
167 // Can't copy this register
173 if (DestRC == Mips::CPURegsRegisterClass)
174 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
176 else if (DestRC == Mips::FGR32RegisterClass)
177 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
178 else if (DestRC == Mips::AFGR64RegisterClass)
179 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
180 else if (DestRC == Mips::CCRRegisterClass)
181 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
183 // Can't copy this register
190 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
191 unsigned SrcReg, bool isKill, int FI,
192 const TargetRegisterClass *RC,
193 const TargetRegisterInfo *TRI) const {
195 if (I != MBB.end()) DL = I->getDebugLoc();
197 if (RC == Mips::CPURegsRegisterClass)
198 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
199 .addImm(0).addFrameIndex(FI);
200 else if (RC == Mips::FGR32RegisterClass)
201 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
202 .addImm(0).addFrameIndex(FI);
203 else if (RC == Mips::AFGR64RegisterClass) {
204 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
205 BuildMI(MBB, I, DL, get(Mips::SDC1))
206 .addReg(SrcReg, getKillRegState(isKill))
207 .addImm(0).addFrameIndex(FI);
209 const TargetRegisterInfo *TRI =
210 MBB.getParent()->getTarget().getRegisterInfo();
211 const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
212 BuildMI(MBB, I, DL, get(Mips::SWC1))
213 .addReg(SubSet[0], getKillRegState(isKill))
214 .addImm(0).addFrameIndex(FI);
215 BuildMI(MBB, I, DL, get(Mips::SWC1))
216 .addReg(SubSet[1], getKillRegState(isKill))
217 .addImm(4).addFrameIndex(FI);
220 llvm_unreachable("Register class not handled!");
224 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
225 unsigned DestReg, int FI,
226 const TargetRegisterClass *RC,
227 const TargetRegisterInfo *TRI) const
230 if (I != MBB.end()) DL = I->getDebugLoc();
232 if (RC == Mips::CPURegsRegisterClass)
233 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
234 else if (RC == Mips::FGR32RegisterClass)
235 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
236 else if (RC == Mips::AFGR64RegisterClass) {
237 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
238 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
240 const TargetRegisterInfo *TRI =
241 MBB.getParent()->getTarget().getRegisterInfo();
242 const unsigned *SubSet = TRI->getSubRegisters(DestReg);
243 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
244 .addImm(0).addFrameIndex(FI);
245 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
246 .addImm(4).addFrameIndex(FI);
249 llvm_unreachable("Register class not handled!");
252 MachineInstr *MipsInstrInfo::
253 foldMemoryOperandImpl(MachineFunction &MF,
255 const SmallVectorImpl<unsigned> &Ops, int FI) const
257 if (Ops.size() != 1) return NULL;
259 MachineInstr *NewMI = NULL;
261 switch (MI->getOpcode()) {
263 if ((MI->getOperand(0).isReg()) &&
264 (MI->getOperand(1).isReg()) &&
265 (MI->getOperand(1).getReg() == Mips::ZERO) &&
266 (MI->getOperand(2).isReg())) {
267 if (Ops[0] == 0) { // COPY -> STORE
268 unsigned SrcReg = MI->getOperand(2).getReg();
269 bool isKill = MI->getOperand(2).isKill();
270 bool isUndef = MI->getOperand(2).isUndef();
271 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
272 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
273 .addImm(0).addFrameIndex(FI);
274 } else { // COPY -> LOAD
275 unsigned DstReg = MI->getOperand(0).getReg();
276 bool isDead = MI->getOperand(0).isDead();
277 bool isUndef = MI->getOperand(0).isUndef();
278 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
279 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
280 getUndefRegState(isUndef))
281 .addImm(0).addFrameIndex(FI);
287 if ((MI->getOperand(0).isReg()) &&
288 (MI->getOperand(1).isReg())) {
289 const TargetRegisterClass
290 *RC = RI.getRegClass(MI->getOperand(0).getReg());
291 unsigned StoreOpc, LoadOpc;
292 bool IsMips1 = TM.getSubtarget<MipsSubtarget>().isMips1();
294 if (RC == Mips::FGR32RegisterClass) {
295 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
297 assert(RC == Mips::AFGR64RegisterClass);
298 // Mips1 doesn't have ldc/sdc instructions.
300 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
303 if (Ops[0] == 0) { // COPY -> STORE
304 unsigned SrcReg = MI->getOperand(1).getReg();
305 bool isKill = MI->getOperand(1).isKill();
306 bool isUndef = MI->getOperand(2).isUndef();
307 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
308 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
309 .addImm(0).addFrameIndex(FI) ;
310 } else { // COPY -> LOAD
311 unsigned DstReg = MI->getOperand(0).getReg();
312 bool isDead = MI->getOperand(0).isDead();
313 bool isUndef = MI->getOperand(0).isUndef();
314 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
315 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
316 getUndefRegState(isUndef))
317 .addImm(0).addFrameIndex(FI);
326 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 /// GetCondFromBranchOpc - Return the Mips CC that matches
331 /// the correspondent Branch instruction opcode.
332 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
335 default: return Mips::COND_INVALID;
336 case Mips::BEQ : return Mips::COND_E;
337 case Mips::BNE : return Mips::COND_NE;
338 case Mips::BGTZ : return Mips::COND_GZ;
339 case Mips::BGEZ : return Mips::COND_GEZ;
340 case Mips::BLTZ : return Mips::COND_LZ;
341 case Mips::BLEZ : return Mips::COND_LEZ;
343 // We dont do fp branch analysis yet!
345 case Mips::BC1F : return Mips::COND_INVALID;
349 /// GetCondBranchFromCond - Return the Branch instruction
350 /// opcode that matches the cc.
351 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
354 default: llvm_unreachable("Illegal condition code!");
355 case Mips::COND_E : return Mips::BEQ;
356 case Mips::COND_NE : return Mips::BNE;
357 case Mips::COND_GZ : return Mips::BGTZ;
358 case Mips::COND_GEZ : return Mips::BGEZ;
359 case Mips::COND_LZ : return Mips::BLTZ;
360 case Mips::COND_LEZ : return Mips::BLEZ;
365 case Mips::FCOND_UEQ:
366 case Mips::FCOND_OLT:
367 case Mips::FCOND_ULT:
368 case Mips::FCOND_OLE:
369 case Mips::FCOND_ULE:
371 case Mips::FCOND_NGLE:
372 case Mips::FCOND_SEQ:
373 case Mips::FCOND_NGL:
375 case Mips::FCOND_NGE:
377 case Mips::FCOND_NGT: return Mips::BC1T;
381 case Mips::FCOND_NEQ:
382 case Mips::FCOND_OGL:
383 case Mips::FCOND_UGE:
384 case Mips::FCOND_OGE:
385 case Mips::FCOND_UGT:
386 case Mips::FCOND_OGT:
388 case Mips::FCOND_GLE:
389 case Mips::FCOND_SNE:
391 case Mips::FCOND_NLT:
393 case Mips::FCOND_NLE:
394 case Mips::FCOND_GT: return Mips::BC1F;
398 /// GetOppositeBranchCondition - Return the inverse of the specified
399 /// condition, e.g. turning COND_E to COND_NE.
400 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
403 default: llvm_unreachable("Illegal condition code!");
404 case Mips::COND_E : return Mips::COND_NE;
405 case Mips::COND_NE : return Mips::COND_E;
406 case Mips::COND_GZ : return Mips::COND_LEZ;
407 case Mips::COND_GEZ : return Mips::COND_LZ;
408 case Mips::COND_LZ : return Mips::COND_GEZ;
409 case Mips::COND_LEZ : return Mips::COND_GZ;
410 case Mips::FCOND_F : return Mips::FCOND_T;
411 case Mips::FCOND_UN : return Mips::FCOND_OR;
412 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
413 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
414 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
415 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
416 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
417 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
418 case Mips::FCOND_SF: return Mips::FCOND_ST;
419 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
420 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
421 case Mips::FCOND_NGL: return Mips::FCOND_GL;
422 case Mips::FCOND_LT: return Mips::FCOND_NLT;
423 case Mips::FCOND_NGE: return Mips::FCOND_GE;
424 case Mips::FCOND_LE: return Mips::FCOND_NLE;
425 case Mips::FCOND_NGT: return Mips::FCOND_GT;
429 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
430 MachineBasicBlock *&TBB,
431 MachineBasicBlock *&FBB,
432 SmallVectorImpl<MachineOperand> &Cond,
433 bool AllowModify) const
435 // If the block has no terminators, it just falls into the block after it.
436 MachineBasicBlock::iterator I = MBB.end();
437 if (I == MBB.begin())
440 while (I->isDebugValue()) {
441 if (I == MBB.begin())
445 if (!isUnpredicatedTerminator(I))
448 // Get the last instruction in the block.
449 MachineInstr *LastInst = I;
451 // If there is only one terminator instruction, process it.
452 unsigned LastOpc = LastInst->getOpcode();
453 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
454 if (!LastInst->getDesc().isBranch())
457 // Unconditional branch
458 if (LastOpc == Mips::J) {
459 TBB = LastInst->getOperand(0).getMBB();
463 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
464 if (BranchCode == Mips::COND_INVALID)
465 return true; // Can't handle indirect branch.
467 // Conditional branch
468 // Block ends with fall-through condbranch.
469 if (LastOpc != Mips::COND_INVALID) {
470 int LastNumOp = LastInst->getNumOperands();
472 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
473 Cond.push_back(MachineOperand::CreateImm(BranchCode));
475 for (int i=0; i<LastNumOp-1; i++) {
476 Cond.push_back(LastInst->getOperand(i));
483 // Get the instruction before it if it is a terminator.
484 MachineInstr *SecondLastInst = I;
486 // If there are three terminators, we don't know what sort of block this is.
487 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
490 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
491 unsigned SecondLastOpc = SecondLastInst->getOpcode();
492 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
494 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
495 int SecondNumOp = SecondLastInst->getNumOperands();
497 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
498 Cond.push_back(MachineOperand::CreateImm(BranchCode));
500 for (int i=0; i<SecondNumOp-1; i++) {
501 Cond.push_back(SecondLastInst->getOperand(i));
504 FBB = LastInst->getOperand(0).getMBB();
508 // If the block ends with two unconditional branches, handle it. The last
509 // one is not executed, so remove it.
510 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
511 TBB = SecondLastInst->getOperand(0).getMBB();
514 I->eraseFromParent();
518 // Otherwise, can't handle this.
522 unsigned MipsInstrInfo::
523 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
524 MachineBasicBlock *FBB,
525 const SmallVectorImpl<MachineOperand> &Cond) const {
526 // FIXME this should probably have a DebugLoc argument
528 // Shouldn't be a fall through.
529 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
530 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
531 "Mips branch conditions can have two|three components!");
533 if (FBB == 0) { // One way branch.
535 // Unconditional branch?
536 BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
538 // Conditional branch.
539 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
540 const TargetInstrDesc &TID = get(Opc);
542 if (TID.getNumOperands() == 3)
543 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
544 .addReg(Cond[2].getReg())
547 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
554 // Two-way Conditional branch.
555 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
556 const TargetInstrDesc &TID = get(Opc);
558 if (TID.getNumOperands() == 3)
559 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
562 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
564 BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
568 unsigned MipsInstrInfo::
569 RemoveBranch(MachineBasicBlock &MBB) const
571 MachineBasicBlock::iterator I = MBB.end();
572 if (I == MBB.begin()) return 0;
574 while (I->isDebugValue()) {
575 if (I == MBB.begin())
579 if (I->getOpcode() != Mips::J &&
580 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
583 // Remove the branch.
584 I->eraseFromParent();
588 if (I == MBB.begin()) return 1;
590 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
593 // Remove the branch.
594 I->eraseFromParent();
598 /// ReverseBranchCondition - Return the inverse opcode of the
599 /// specified Branch instruction.
601 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
603 assert( (Cond.size() == 3 || Cond.size() == 2) &&
604 "Invalid Mips branch condition!");
605 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
609 /// getGlobalBaseReg - Return a virtual register initialized with the
610 /// the global base register value. Output instructions required to
611 /// initialize the register in the function entry block, if necessary.
613 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
614 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
615 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
616 if (GlobalBaseReg != 0)
617 return GlobalBaseReg;
619 // Insert the set of GlobalBaseReg into the first MBB of the function
620 MachineBasicBlock &FirstMBB = MF->front();
621 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
622 MachineRegisterInfo &RegInfo = MF->getRegInfo();
623 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
625 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
626 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
627 Mips::CPURegsRegisterClass,
628 Mips::CPURegsRegisterClass);
629 assert(Ok && "Couldn't assign to global base register!");
630 Ok = Ok; // Silence warning when assertions are turned off.
631 RegInfo.addLiveIn(Mips::GP);
633 MipsFI->setGlobalBaseReg(GlobalBaseReg);
634 return GlobalBaseReg;