1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
25 #define GET_INSTRINFO_CTOR
26 #include "MipsGenInstrInfo.inc"
30 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32 TM(tm), UncondBrOpc(UncondBr) {}
34 const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) {
35 if (TM.getSubtargetImpl()->inMips16Mode())
36 return llvm::createMips16InstrInfo(TM);
38 return llvm::createMipsSEInstrInfo(TM);
41 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
42 return op.isImm() && op.getImm() == 0;
45 /// insertNoop - If data hazard condition is found insert the target nop
48 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
51 BuildMI(MBB, MI, DL, get(Mips::NOP));
54 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
55 unsigned Flag) const {
56 MachineFunction &MF = *MBB.getParent();
57 MachineFrameInfo &MFI = *MF.getFrameInfo();
58 unsigned Align = MFI.getObjectAlignment(FI);
60 return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
61 MFI.getObjectSize(FI), Align);
65 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
66 uint64_t Offset, const MDNode *MDPtr,
68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
69 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
73 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
78 MachineBasicBlock *&BB,
79 SmallVectorImpl<MachineOperand> &Cond) const {
80 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
81 int NumOp = Inst->getNumExplicitOperands();
83 // for both int and fp branches, the last explicit operand is the
85 BB = Inst->getOperand(NumOp-1).getMBB();
86 Cond.push_back(MachineOperand::CreateImm(Opc));
88 for (int i=0; i<NumOp-1; i++)
89 Cond.push_back(Inst->getOperand(i));
92 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
93 MachineBasicBlock *&TBB,
94 MachineBasicBlock *&FBB,
95 SmallVectorImpl<MachineOperand> &Cond,
96 bool AllowModify) const
99 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
101 // Skip all the debug instructions.
102 while (I != REnd && I->isDebugValue())
105 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
106 // If this block ends with no branches (it just falls through to its succ)
107 // just return false, leaving TBB/FBB null.
112 MachineInstr *LastInst = &*I;
113 unsigned LastOpc = LastInst->getOpcode();
115 // Not an analyzable branch (must be an indirect jump).
116 if (!GetAnalyzableBrOpc(LastOpc))
119 // Get the second to last instruction in the block.
120 unsigned SecondLastOpc = 0;
121 MachineInstr *SecondLastInst = NULL;
124 SecondLastInst = &*I;
125 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
127 // Not an analyzable branch (must be an indirect jump).
128 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
132 // If there is only one terminator instruction, process it.
133 if (!SecondLastOpc) {
134 // Unconditional branch
135 if (LastOpc == UncondBrOpc) {
136 TBB = LastInst->getOperand(0).getMBB();
140 // Conditional branch
141 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
145 // If we reached here, there are two branches.
146 // If there are three terminators, we don't know what sort of block this is.
147 if (++I != REnd && isUnpredicatedTerminator(&*I))
150 // If second to last instruction is an unconditional branch,
151 // analyze it and remove the last instruction.
152 if (SecondLastOpc == UncondBrOpc) {
153 // Return if the last instruction cannot be removed.
157 TBB = SecondLastInst->getOperand(0).getMBB();
158 LastInst->eraseFromParent();
162 // Conditional branch followed by an unconditional branch.
163 // The last one must be unconditional.
164 if (LastOpc != UncondBrOpc)
167 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
168 FBB = LastInst->getOperand(0).getMBB();
173 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
174 MachineBasicBlock *TBB, DebugLoc DL,
175 const SmallVectorImpl<MachineOperand>& Cond)
177 unsigned Opc = Cond[0].getImm();
178 const MCInstrDesc &MCID = get(Opc);
179 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
181 for (unsigned i = 1; i < Cond.size(); ++i) {
183 MIB.addReg(Cond[i].getReg());
184 else if (Cond[i].isImm())
185 MIB.addImm(Cond[i].getImm());
187 assert(true && "Cannot copy operand");
192 unsigned MipsInstrInfo::
193 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
194 MachineBasicBlock *FBB,
195 const SmallVectorImpl<MachineOperand> &Cond,
197 // Shouldn't be a fall through.
198 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
200 // # of condition operands:
201 // Unconditional branches: 0
202 // Floating point branches: 1 (opc)
203 // Int BranchZero: 2 (opc, reg)
204 // Int Branch: 3 (opc, reg0, reg1)
205 assert((Cond.size() <= 3) &&
206 "# of Mips branch conditions must be <= 3!");
208 // Two-way Conditional branch.
210 BuildCondBr(MBB, TBB, DL, Cond);
211 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
216 // Unconditional branch.
218 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
219 else // Conditional branch.
220 BuildCondBr(MBB, TBB, DL, Cond);
224 unsigned MipsInstrInfo::
225 RemoveBranch(MachineBasicBlock &MBB) const
227 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
228 MachineBasicBlock::reverse_iterator FirstBr;
231 // Skip all the debug instructions.
232 while (I != REnd && I->isDebugValue())
237 // Up to 2 branches are removed.
238 // Note that indirect branches are not removed.
239 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
240 if (!GetAnalyzableBrOpc(I->getOpcode()))
243 MBB.erase(I.base(), FirstBr.base());
248 /// ReverseBranchCondition - Return the inverse opcode of the
249 /// specified Branch instruction.
251 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
253 assert( (Cond.size() && Cond.size() <= 3) &&
254 "Invalid Mips branch condition!");
255 Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
259 /// Return the number of bytes of code the specified instruction may be.
260 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
261 switch (MI->getOpcode()) {
263 return MI->getDesc().getSize();
264 case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
265 const MachineFunction *MF = MI->getParent()->getParent();
266 const char *AsmStr = MI->getOperand(0).getSymbolName();
267 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());