1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsAnalyzeImmediate.h"
15 #include "MipsInstrInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "MipsMachineFunction.h"
18 #include "InstPrinter/MipsInstPrinter.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/ADT/STLExtras.h"
25 #define GET_INSTRINFO_CTOR
26 #include "MipsGenInstrInfo.inc"
30 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
31 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32 TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
33 RI(*TM.getSubtargetImpl(), *this),
34 UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {}
36 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
40 static bool isZeroImm(const MachineOperand &op) {
41 return op.isImm() && op.getImm() == 0;
44 /// isLoadFromStackSlot - If the specified machine instruction is a direct
45 /// load from a stack slot, return the virtual or physical register number of
46 /// the destination along with the FrameIndex of the loaded stack slot. If
47 /// not, return 0. This predicate must return 0 if the instruction has
48 /// any side effects other than loading from the stack slot.
49 unsigned MipsInstrInfo::
50 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
52 unsigned Opc = MI->getOpcode();
54 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
55 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
56 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
57 (Opc == Mips::LDC164_P8)) {
58 if ((MI->getOperand(1).isFI()) && // is a stack slot
59 (MI->getOperand(2).isImm()) && // the imm is zero
60 (isZeroImm(MI->getOperand(2)))) {
61 FrameIndex = MI->getOperand(1).getIndex();
62 return MI->getOperand(0).getReg();
69 /// isStoreToStackSlot - If the specified machine instruction is a direct
70 /// store to a stack slot, return the virtual or physical register number of
71 /// the source reg along with the FrameIndex of the loaded stack slot. If
72 /// not, return 0. This predicate must return 0 if the instruction has
73 /// any side effects other than storing to the stack slot.
74 unsigned MipsInstrInfo::
75 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
77 unsigned Opc = MI->getOpcode();
79 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
80 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
81 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
82 (Opc == Mips::SDC164_P8)) {
83 if ((MI->getOperand(1).isFI()) && // is a stack slot
84 (MI->getOperand(2).isImm()) && // the imm is zero
85 (isZeroImm(MI->getOperand(2)))) {
86 FrameIndex = MI->getOperand(1).getIndex();
87 return MI->getOperand(0).getReg();
93 /// insertNoop - If data hazard condition is found insert the target nop
96 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
99 BuildMI(MBB, MI, DL, get(Mips::NOP));
103 copyPhysReg(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator I, DebugLoc DL,
105 unsigned DestReg, unsigned SrcReg,
106 bool KillSrc) const {
107 unsigned Opc = 0, ZeroReg = 0;
109 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
110 if (Mips::CPURegsRegClass.contains(SrcReg))
111 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
112 else if (Mips::CCRRegClass.contains(SrcReg))
114 else if (Mips::FGR32RegClass.contains(SrcReg))
116 else if (SrcReg == Mips::HI)
117 Opc = Mips::MFHI, SrcReg = 0;
118 else if (SrcReg == Mips::LO)
119 Opc = Mips::MFLO, SrcReg = 0;
121 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
122 if (Mips::CCRRegClass.contains(DestReg))
124 else if (Mips::FGR32RegClass.contains(DestReg))
126 else if (DestReg == Mips::HI)
127 Opc = Mips::MTHI, DestReg = 0;
128 else if (DestReg == Mips::LO)
129 Opc = Mips::MTLO, DestReg = 0;
131 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
133 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
134 Opc = Mips::FMOV_D32;
135 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
136 Opc = Mips::FMOV_D64;
137 else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
138 Opc = Mips::MOVCCRToCCR;
139 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
140 if (Mips::CPU64RegsRegClass.contains(SrcReg))
141 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
142 else if (SrcReg == Mips::HI64)
143 Opc = Mips::MFHI64, SrcReg = 0;
144 else if (SrcReg == Mips::LO64)
145 Opc = Mips::MFLO64, SrcReg = 0;
146 else if (Mips::FGR64RegClass.contains(SrcReg))
149 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
150 if (DestReg == Mips::HI64)
151 Opc = Mips::MTHI64, DestReg = 0;
152 else if (DestReg == Mips::LO64)
153 Opc = Mips::MTLO64, DestReg = 0;
154 else if (Mips::FGR64RegClass.contains(DestReg))
158 assert(Opc && "Cannot copy registers");
160 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
163 MIB.addReg(DestReg, RegState::Define);
169 MIB.addReg(SrcReg, getKillRegState(KillSrc));
172 static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
174 MachineFunction &MF = *MBB.getParent();
175 MachineFrameInfo &MFI = *MF.getFrameInfo();
176 unsigned Align = MFI.getObjectAlignment(FI);
178 return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
179 MFI.getObjectSize(FI), Align);
183 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184 unsigned SrcReg, bool isKill, int FI,
185 const TargetRegisterClass *RC,
186 const TargetRegisterInfo *TRI) const {
188 if (I != MBB.end()) DL = I->getDebugLoc();
189 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
193 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
194 Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
195 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
196 Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
197 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
198 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
199 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
201 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
202 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
204 assert(Opc && "Register class not handled!");
205 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
206 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
210 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
211 unsigned DestReg, int FI,
212 const TargetRegisterClass *RC,
213 const TargetRegisterInfo *TRI) const
216 if (I != MBB.end()) DL = I->getDebugLoc();
217 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
220 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
221 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
222 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
223 Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
224 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
225 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
226 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
228 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
229 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
231 assert(Opc && "Register class not handled!");
232 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
236 void MipsInstrInfo::ExpandRetRA(MachineBasicBlock &MBB,
237 MachineBasicBlock::iterator I,
238 unsigned Opc) const {
239 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(Opc))
243 void MipsInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
244 MachineBasicBlock::iterator I) const {
245 const TargetInstrInfo *TII = TM.getInstrInfo();
246 unsigned DstReg = I->getOperand(0).getReg();
247 unsigned SrcReg = I->getOperand(1).getReg();
248 unsigned N = I->getOperand(2).getImm();
249 const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
250 DebugLoc dl = I->getDebugLoc();
252 assert(N < 2 && "Invalid immediate");
253 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
254 unsigned SubReg = TM.getRegisterInfo()->getSubReg(SrcReg, SubIdx);
256 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
259 void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
260 MachineBasicBlock::iterator I) const {
261 const TargetInstrInfo *TII = TM.getInstrInfo();
262 unsigned DstReg = I->getOperand(0).getReg();
263 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
264 const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
265 DebugLoc dl = I->getDebugLoc();
266 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
270 BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpeven))
272 BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpodd))
276 bool MipsInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
277 MachineBasicBlock &MBB = *MI->getParent();
279 switch(MI->getDesc().getOpcode()) {
283 ExpandRetRA(MBB, MI, Mips::RET);
286 ExpandRetRA(MBB, MI, Mips::RET16);
288 case Mips::BuildPairF64:
289 ExpandBuildPairF64(MBB, MI);
291 case Mips::ExtractElementF64:
292 ExpandExtractElementF64(MBB, MI);
301 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
302 uint64_t Offset, const MDNode *MDPtr,
304 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
305 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
309 //===----------------------------------------------------------------------===//
311 //===----------------------------------------------------------------------===//
313 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
314 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
315 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
316 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
317 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
318 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
323 /// GetOppositeBranchOpc - Return the inverse of the specified
324 /// opcode, e.g. turning BEQ to BNE.
325 unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
328 default: llvm_unreachable("Illegal opcode!");
329 case Mips::BEQ: return Mips::BNE;
330 case Mips::BNE: return Mips::BEQ;
331 case Mips::BGTZ: return Mips::BLEZ;
332 case Mips::BGEZ: return Mips::BLTZ;
333 case Mips::BLTZ: return Mips::BGEZ;
334 case Mips::BLEZ: return Mips::BGTZ;
335 case Mips::BEQ64: return Mips::BNE64;
336 case Mips::BNE64: return Mips::BEQ64;
337 case Mips::BGTZ64: return Mips::BLEZ64;
338 case Mips::BGEZ64: return Mips::BLTZ64;
339 case Mips::BLTZ64: return Mips::BGEZ64;
340 case Mips::BLEZ64: return Mips::BGTZ64;
341 case Mips::BC1T: return Mips::BC1F;
342 case Mips::BC1F: return Mips::BC1T;
346 static void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
347 MachineBasicBlock *&BB,
348 SmallVectorImpl<MachineOperand> &Cond) {
349 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
350 int NumOp = Inst->getNumExplicitOperands();
352 // for both int and fp branches, the last explicit operand is the
354 BB = Inst->getOperand(NumOp-1).getMBB();
355 Cond.push_back(MachineOperand::CreateImm(Opc));
357 for (int i=0; i<NumOp-1; i++)
358 Cond.push_back(Inst->getOperand(i));
361 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
362 MachineBasicBlock *&TBB,
363 MachineBasicBlock *&FBB,
364 SmallVectorImpl<MachineOperand> &Cond,
365 bool AllowModify) const
367 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
369 // Skip all the debug instructions.
370 while (I != REnd && I->isDebugValue())
373 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
374 // If this block ends with no branches (it just falls through to its succ)
375 // just return false, leaving TBB/FBB null.
380 MachineInstr *LastInst = &*I;
381 unsigned LastOpc = LastInst->getOpcode();
383 // Not an analyzable branch (must be an indirect jump).
384 if (!GetAnalyzableBrOpc(LastOpc))
387 // Get the second to last instruction in the block.
388 unsigned SecondLastOpc = 0;
389 MachineInstr *SecondLastInst = NULL;
392 SecondLastInst = &*I;
393 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
395 // Not an analyzable branch (must be an indirect jump).
396 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
400 // If there is only one terminator instruction, process it.
401 if (!SecondLastOpc) {
402 // Unconditional branch
403 if (LastOpc == UncondBrOpc) {
404 TBB = LastInst->getOperand(0).getMBB();
408 // Conditional branch
409 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
413 // If we reached here, there are two branches.
414 // If there are three terminators, we don't know what sort of block this is.
415 if (++I != REnd && isUnpredicatedTerminator(&*I))
418 // If second to last instruction is an unconditional branch,
419 // analyze it and remove the last instruction.
420 if (SecondLastOpc == UncondBrOpc) {
421 // Return if the last instruction cannot be removed.
425 TBB = SecondLastInst->getOperand(0).getMBB();
426 LastInst->eraseFromParent();
430 // Conditional branch followed by an unconditional branch.
431 // The last one must be unconditional.
432 if (LastOpc != UncondBrOpc)
435 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
436 FBB = LastInst->getOperand(0).getMBB();
441 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
442 MachineBasicBlock *TBB, DebugLoc DL,
443 const SmallVectorImpl<MachineOperand>& Cond)
445 unsigned Opc = Cond[0].getImm();
446 const MCInstrDesc &MCID = get(Opc);
447 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
449 for (unsigned i = 1; i < Cond.size(); ++i)
450 MIB.addReg(Cond[i].getReg());
455 unsigned MipsInstrInfo::
456 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
457 MachineBasicBlock *FBB,
458 const SmallVectorImpl<MachineOperand> &Cond,
460 // Shouldn't be a fall through.
461 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
463 // # of condition operands:
464 // Unconditional branches: 0
465 // Floating point branches: 1 (opc)
466 // Int BranchZero: 2 (opc, reg)
467 // Int Branch: 3 (opc, reg0, reg1)
468 assert((Cond.size() <= 3) &&
469 "# of Mips branch conditions must be <= 3!");
471 // Two-way Conditional branch.
473 BuildCondBr(MBB, TBB, DL, Cond);
474 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
479 // Unconditional branch.
481 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
482 else // Conditional branch.
483 BuildCondBr(MBB, TBB, DL, Cond);
487 unsigned MipsInstrInfo::
488 RemoveBranch(MachineBasicBlock &MBB) const
490 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
491 MachineBasicBlock::reverse_iterator FirstBr;
494 // Skip all the debug instructions.
495 while (I != REnd && I->isDebugValue())
500 // Up to 2 branches are removed.
501 // Note that indirect branches are not removed.
502 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
503 if (!GetAnalyzableBrOpc(I->getOpcode()))
506 MBB.erase(I.base(), FirstBr.base());
511 /// ReverseBranchCondition - Return the inverse opcode of the
512 /// specified Branch instruction.
514 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
516 assert( (Cond.size() && Cond.size() <= 3) &&
517 "Invalid Mips branch condition!");
518 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
522 /// Return the number of bytes of code the specified instruction may be.
523 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
524 switch (MI->getOpcode()) {
526 return MI->getDesc().getSize();
527 case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
528 const MachineFunction *MF = MI->getParent()->getParent();
529 const char *AsmStr = MI->getOperand(0).getSymbolName();
530 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
536 llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
537 MachineBasicBlock& MBB,
538 MachineBasicBlock::iterator II, DebugLoc DL,
539 bool LastInstrIsADDiu,
540 MipsAnalyzeImmediate::Inst *LastInst) {
541 MipsAnalyzeImmediate AnalyzeImm;
542 unsigned Size = IsN64 ? 64 : 32;
543 unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
544 unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
545 unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
547 const MipsAnalyzeImmediate::InstSeq &Seq =
548 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
549 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
551 if (LastInst && (Seq.size() == 1)) {
556 // The first instruction can be a LUi, which is different from other
557 // instructions (ADDiu, ORI and SLL) in that it does not have a register
559 if (Inst->Opc == LUi)
560 BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
561 .addImm(SignExtend64<16>(Inst->ImmOpnd));
563 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
564 .addImm(SignExtend64<16>(Inst->ImmOpnd));
566 // Build the remaining instructions in Seq. Skip the last instruction if
567 // LastInst is not 0.
568 for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
569 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
570 .addImm(SignExtend64<16>(Inst->ImmOpnd));
575 return Seq.size() - !!LastInst;