1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "MipsGenInstrInfo.inc"
22 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
23 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
24 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
26 static bool isZeroImm(const MachineOperand &op) {
27 return op.isImm() && op.getImm() == 0;
30 /// Return true if the instruction is a register to register move and
31 /// leave the source and dest operands in the passed parameters.
33 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
34 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
36 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
38 // addu $dst, $src, $zero || addu $dst, $zero, $src
39 // or $dst, $src, $zero || or $dst, $zero, $src
40 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
41 if (MI.getOperand(1).getReg() == Mips::ZERO) {
42 DstReg = MI.getOperand(0).getReg();
43 SrcReg = MI.getOperand(2).getReg();
45 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
46 DstReg = MI.getOperand(0).getReg();
47 SrcReg = MI.getOperand(1).getReg();
55 if (MI.getOpcode() == Mips::FMOV_S32 ||
56 MI.getOpcode() == Mips::FMOV_D32 ||
57 MI.getOpcode() == Mips::MFC1 ||
58 MI.getOpcode() == Mips::MTC1 ) {
59 DstReg = MI.getOperand(0).getReg();
60 SrcReg = MI.getOperand(1).getReg();
64 // addiu $dst, $src, 0
65 if (MI.getOpcode() == Mips::ADDiu) {
66 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
67 DstReg = MI.getOperand(0).getReg();
68 SrcReg = MI.getOperand(1).getReg();
75 /// isLoadFromStackSlot - If the specified machine instruction is a direct
76 /// load from a stack slot, return the virtual or physical register number of
77 /// the destination along with the FrameIndex of the loaded stack slot. If
78 /// not, return 0. This predicate must return 0 if the instruction has
79 /// any side effects other than loading from the stack slot.
80 unsigned MipsInstrInfo::
81 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
83 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
84 (MI->getOpcode() == Mips::LDC1)) {
85 if ((MI->getOperand(2).isFI()) && // is a stack slot
86 (MI->getOperand(1).isImm()) && // the imm is zero
87 (isZeroImm(MI->getOperand(1)))) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
96 /// isStoreToStackSlot - If the specified machine instruction is a direct
97 /// store to a stack slot, return the virtual or physical register number of
98 /// the source reg along with the FrameIndex of the loaded stack slot. If
99 /// not, return 0. This predicate must return 0 if the instruction has
100 /// any side effects other than storing to the stack slot.
101 unsigned MipsInstrInfo::
102 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
104 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
105 (MI->getOpcode() == Mips::SDC1)) {
106 if ((MI->getOperand(2).isFI()) && // is a stack slot
107 (MI->getOperand(1).isImm()) && // the imm is zero
108 (isZeroImm(MI->getOperand(1)))) {
109 FrameIndex = MI->getOperand(2).getIndex();
110 return MI->getOperand(0).getReg();
116 /// insertNoop - If data hazard condition is found insert the target nop
119 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
121 DebugLoc DL = DebugLoc::getUnknownLoc();
122 if (MI != MBB.end()) DL = MI->getDebugLoc();
123 BuildMI(MBB, MI, DL, get(Mips::NOP));
127 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
128 unsigned DestReg, unsigned SrcReg,
129 const TargetRegisterClass *DestRC,
130 const TargetRegisterClass *SrcRC) const {
131 DebugLoc DL = DebugLoc::getUnknownLoc();
132 if (I != MBB.end()) DL = I->getDebugLoc();
134 if (DestRC != SrcRC) {
135 // Moves between coprocessors and cpu
136 if ((DestRC == Mips::CPURegsRegisterClass) &&
137 (SrcRC == Mips::FGR32RegisterClass))
138 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
139 else if ((DestRC == Mips::FGR32RegisterClass) &&
140 (SrcRC == Mips::CPURegsRegisterClass))
141 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
143 // Condition registers
144 else if ((SrcRC == Mips::CCRRegisterClass) &&
145 (SrcReg == Mips::FCR31))
146 return true; // This register is used implicitly, no copy needed.
147 else if ((DestRC == Mips::CCRRegisterClass) &&
148 (DestReg == Mips::FCR31))
149 return true; // This register is used implicitly, no copy needed.
151 // Move from/to Hi/Lo registers
152 else if ((DestRC == Mips::HILORegisterClass) &&
153 (SrcRC == Mips::CPURegsRegisterClass)) {
154 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
155 BuildMI(MBB, I, DL, get(Opc), DestReg);
156 } else if ((SrcRC == Mips::HILORegisterClass) &&
157 (DestRC == Mips::CPURegsRegisterClass)) {
158 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
159 BuildMI(MBB, I, DL, get(Opc), DestReg);
161 // Can't copy this register
168 if (DestRC == Mips::CPURegsRegisterClass)
169 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
171 else if (DestRC == Mips::FGR32RegisterClass)
172 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
173 else if (DestRC == Mips::AFGR64RegisterClass)
174 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
176 // Can't copy this register
183 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184 unsigned SrcReg, bool isKill, int FI,
185 const TargetRegisterClass *RC) const
189 DebugLoc DL = DebugLoc::getUnknownLoc();
190 if (I != MBB.end()) DL = I->getDebugLoc();
192 if (RC == Mips::CPURegsRegisterClass)
194 else if (RC == Mips::FGR32RegisterClass)
196 else if (RC == Mips::AFGR64RegisterClass)
199 assert(0 && "Can't store this register to stack slot");
201 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill)
202 .addImm(0).addFrameIndex(FI);
205 void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
206 bool isKill, SmallVectorImpl<MachineOperand> &Addr,
207 const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
210 if (RC == Mips::CPURegsRegisterClass)
212 else if (RC == Mips::FGR32RegisterClass)
214 else if (RC == Mips::AFGR64RegisterClass)
217 assert(0 && "Can't store this register");
219 DebugLoc DL = DebugLoc::getUnknownLoc();
220 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
221 .addReg(SrcReg, false, false, isKill);
222 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
223 MIB.addOperand(Addr[i]);
224 NewMIs.push_back(MIB);
229 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
230 unsigned DestReg, int FI,
231 const TargetRegisterClass *RC) const
234 if (RC == Mips::CPURegsRegisterClass)
236 else if (RC == Mips::FGR32RegisterClass)
238 else if (RC == Mips::AFGR64RegisterClass)
241 assert(0 && "Can't load this register from stack slot");
243 DebugLoc DL = DebugLoc::getUnknownLoc();
244 if (I != MBB.end()) DL = I->getDebugLoc();
245 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
248 void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
249 SmallVectorImpl<MachineOperand> &Addr,
250 const TargetRegisterClass *RC,
251 SmallVectorImpl<MachineInstr*> &NewMIs) const {
253 if (RC == Mips::CPURegsRegisterClass)
255 else if (RC == Mips::FGR32RegisterClass)
257 else if (RC == Mips::AFGR64RegisterClass)
260 assert(0 && "Can't load this register");
262 DebugLoc DL = DebugLoc::getUnknownLoc();
263 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
264 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
265 MIB.addOperand(Addr[i]);
266 NewMIs.push_back(MIB);
270 MachineInstr *MipsInstrInfo::
271 foldMemoryOperandImpl(MachineFunction &MF,
273 const SmallVectorImpl<unsigned> &Ops, int FI) const
275 if (Ops.size() != 1) return NULL;
277 MachineInstr *NewMI = NULL;
279 switch (MI->getOpcode()) {
281 if ((MI->getOperand(0).isReg()) &&
282 (MI->getOperand(1).isReg()) &&
283 (MI->getOperand(1).getReg() == Mips::ZERO) &&
284 (MI->getOperand(2).isReg())) {
285 if (Ops[0] == 0) { // COPY -> STORE
286 unsigned SrcReg = MI->getOperand(2).getReg();
287 bool isKill = MI->getOperand(2).isKill();
288 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
289 .addReg(SrcReg, false, false, isKill)
290 .addImm(0).addFrameIndex(FI);
291 } else { // COPY -> LOAD
292 unsigned DstReg = MI->getOperand(0).getReg();
293 bool isDead = MI->getOperand(0).isDead();
294 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
295 .addReg(DstReg, true, false, false, isDead)
296 .addImm(0).addFrameIndex(FI);
302 if ((MI->getOperand(0).isReg()) &&
303 (MI->getOperand(1).isReg())) {
304 const TargetRegisterClass
305 *RC = RI.getRegClass(MI->getOperand(0).getReg());
306 unsigned StoreOpc, LoadOpc;
308 if (RC == Mips::FGR32RegisterClass) {
309 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
310 } else if (RC == Mips::AFGR64RegisterClass) {
311 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
313 assert(0 && "foldMemoryOperandImpl register unknown");
315 if (Ops[0] == 0) { // COPY -> STORE
316 unsigned SrcReg = MI->getOperand(1).getReg();
317 bool isKill = MI->getOperand(1).isKill();
318 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
319 .addReg(SrcReg, false, false, isKill)
320 .addImm(0).addFrameIndex(FI) ;
321 } else { // COPY -> LOAD
322 unsigned DstReg = MI->getOperand(0).getReg();
323 bool isDead = MI->getOperand(0).isDead();
324 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
325 .addReg(DstReg, true, false, false, isDead)
326 .addImm(0).addFrameIndex(FI);
335 //===----------------------------------------------------------------------===//
337 //===----------------------------------------------------------------------===//
339 /// GetCondFromBranchOpc - Return the Mips CC that matches
340 /// the correspondent Branch instruction opcode.
341 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
344 default: return Mips::COND_INVALID;
345 case Mips::BEQ : return Mips::COND_E;
346 case Mips::BNE : return Mips::COND_NE;
347 case Mips::BGTZ : return Mips::COND_GZ;
348 case Mips::BGEZ : return Mips::COND_GEZ;
349 case Mips::BLTZ : return Mips::COND_LZ;
350 case Mips::BLEZ : return Mips::COND_LEZ;
352 // We dont do fp branch analysis yet!
354 case Mips::BC1F : return Mips::COND_INVALID;
358 /// GetCondBranchFromCond - Return the Branch instruction
359 /// opcode that matches the cc.
360 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
363 default: assert(0 && "Illegal condition code!");
364 case Mips::COND_E : return Mips::BEQ;
365 case Mips::COND_NE : return Mips::BNE;
366 case Mips::COND_GZ : return Mips::BGTZ;
367 case Mips::COND_GEZ : return Mips::BGEZ;
368 case Mips::COND_LZ : return Mips::BLTZ;
369 case Mips::COND_LEZ : return Mips::BLEZ;
374 case Mips::FCOND_UEQ:
375 case Mips::FCOND_OLT:
376 case Mips::FCOND_ULT:
377 case Mips::FCOND_OLE:
378 case Mips::FCOND_ULE:
380 case Mips::FCOND_NGLE:
381 case Mips::FCOND_SEQ:
382 case Mips::FCOND_NGL:
384 case Mips::FCOND_NGE:
386 case Mips::FCOND_NGT: return Mips::BC1T;
390 case Mips::FCOND_NEQ:
391 case Mips::FCOND_OGL:
392 case Mips::FCOND_UGE:
393 case Mips::FCOND_OGE:
394 case Mips::FCOND_UGT:
395 case Mips::FCOND_OGT:
397 case Mips::FCOND_GLE:
398 case Mips::FCOND_SNE:
400 case Mips::FCOND_NLT:
402 case Mips::FCOND_NLE:
403 case Mips::FCOND_GT: return Mips::BC1F;
407 /// GetOppositeBranchCondition - Return the inverse of the specified
408 /// condition, e.g. turning COND_E to COND_NE.
409 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
412 default: assert(0 && "Illegal condition code!");
413 case Mips::COND_E : return Mips::COND_NE;
414 case Mips::COND_NE : return Mips::COND_E;
415 case Mips::COND_GZ : return Mips::COND_LEZ;
416 case Mips::COND_GEZ : return Mips::COND_LZ;
417 case Mips::COND_LZ : return Mips::COND_GEZ;
418 case Mips::COND_LEZ : return Mips::COND_GZ;
419 case Mips::FCOND_F : return Mips::FCOND_T;
420 case Mips::FCOND_UN : return Mips::FCOND_OR;
421 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
422 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
423 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
424 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
425 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
426 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
427 case Mips::FCOND_SF: return Mips::FCOND_ST;
428 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
429 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
430 case Mips::FCOND_NGL: return Mips::FCOND_GL;
431 case Mips::FCOND_LT: return Mips::FCOND_NLT;
432 case Mips::FCOND_NGE: return Mips::FCOND_GE;
433 case Mips::FCOND_LE: return Mips::FCOND_NLE;
434 case Mips::FCOND_NGT: return Mips::FCOND_GT;
438 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
439 MachineBasicBlock *&TBB,
440 MachineBasicBlock *&FBB,
441 SmallVectorImpl<MachineOperand> &Cond,
442 bool AllowModify) const
444 // If the block has no terminators, it just falls into the block after it.
445 MachineBasicBlock::iterator I = MBB.end();
446 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
449 // Get the last instruction in the block.
450 MachineInstr *LastInst = I;
452 // If there is only one terminator instruction, process it.
453 unsigned LastOpc = LastInst->getOpcode();
454 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
455 if (!LastInst->getDesc().isBranch())
458 // Unconditional branch
459 if (LastOpc == Mips::J) {
460 TBB = LastInst->getOperand(0).getMBB();
464 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
465 if (BranchCode == Mips::COND_INVALID)
466 return true; // Can't handle indirect branch.
468 // Conditional branch
469 // Block ends with fall-through condbranch.
470 if (LastOpc != Mips::COND_INVALID) {
471 int LastNumOp = LastInst->getNumOperands();
473 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
474 Cond.push_back(MachineOperand::CreateImm(BranchCode));
476 for (int i=0; i<LastNumOp-1; i++) {
477 Cond.push_back(LastInst->getOperand(i));
484 // Get the instruction before it if it is a terminator.
485 MachineInstr *SecondLastInst = I;
487 // If there are three terminators, we don't know what sort of block this is.
488 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
491 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
492 unsigned SecondLastOpc = SecondLastInst->getOpcode();
493 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
495 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
496 int SecondNumOp = SecondLastInst->getNumOperands();
498 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
499 Cond.push_back(MachineOperand::CreateImm(BranchCode));
501 for (int i=0; i<SecondNumOp-1; i++) {
502 Cond.push_back(SecondLastInst->getOperand(i));
505 FBB = LastInst->getOperand(0).getMBB();
509 // If the block ends with two unconditional branches, handle it. The last
510 // one is not executed, so remove it.
511 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
512 TBB = SecondLastInst->getOperand(0).getMBB();
515 I->eraseFromParent();
519 // Otherwise, can't handle this.
523 unsigned MipsInstrInfo::
524 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
525 MachineBasicBlock *FBB,
526 const SmallVectorImpl<MachineOperand> &Cond) const {
527 // FIXME this should probably have a DebugLoc argument
528 DebugLoc dl = DebugLoc::getUnknownLoc();
529 // Shouldn't be a fall through.
530 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
531 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
532 "Mips branch conditions can have two|three components!");
534 if (FBB == 0) { // One way branch.
536 // Unconditional branch?
537 BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
539 // Conditional branch.
540 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
541 const TargetInstrDesc &TID = get(Opc);
543 if (TID.getNumOperands() == 3)
544 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
545 .addReg(Cond[2].getReg())
548 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
555 // Two-way Conditional branch.
556 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
557 const TargetInstrDesc &TID = get(Opc);
559 if (TID.getNumOperands() == 3)
560 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
563 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
565 BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
569 unsigned MipsInstrInfo::
570 RemoveBranch(MachineBasicBlock &MBB) const
572 MachineBasicBlock::iterator I = MBB.end();
573 if (I == MBB.begin()) return 0;
575 if (I->getOpcode() != Mips::J &&
576 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
579 // Remove the branch.
580 I->eraseFromParent();
584 if (I == MBB.begin()) return 1;
586 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
589 // Remove the branch.
590 I->eraseFromParent();
594 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
595 /// fall-through into its successor block.
597 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
599 if (MBB.empty()) return false;
601 switch (MBB.back().getOpcode()) {
602 case Mips::RET: // Return.
603 case Mips::JR: // Indirect branch.
604 case Mips::J: // Uncond branch.
606 default: return false;
610 /// ReverseBranchCondition - Return the inverse opcode of the
611 /// specified Branch instruction.
613 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
615 assert( (Cond.size() == 3 || Cond.size() == 2) &&
616 "Invalid Mips branch condition!");
617 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));