1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
24 #define GET_INSTRINFO_CTOR
25 #include "MipsGenInstrInfo.inc"
29 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
30 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
31 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
34 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
38 static bool isZeroImm(const MachineOperand &op) {
39 return op.isImm() && op.getImm() == 0;
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 unsigned MipsInstrInfo::
48 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
50 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
51 (MI->getOpcode() == Mips::LDC1)) {
52 if ((MI->getOperand(1).isFI()) && // is a stack slot
53 (MI->getOperand(2).isImm()) && // the imm is zero
54 (isZeroImm(MI->getOperand(2)))) {
55 FrameIndex = MI->getOperand(1).getIndex();
56 return MI->getOperand(0).getReg();
63 /// isStoreToStackSlot - If the specified machine instruction is a direct
64 /// store to a stack slot, return the virtual or physical register number of
65 /// the source reg along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than storing to the stack slot.
68 unsigned MipsInstrInfo::
69 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
71 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
72 (MI->getOpcode() == Mips::SDC1)) {
73 if ((MI->getOperand(1).isFI()) && // is a stack slot
74 (MI->getOperand(2).isImm()) && // the imm is zero
75 (isZeroImm(MI->getOperand(2)))) {
76 FrameIndex = MI->getOperand(1).getIndex();
77 return MI->getOperand(0).getReg();
83 /// insertNoop - If data hazard condition is found insert the target nop
86 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
89 BuildMI(MBB, MI, DL, get(Mips::NOP));
93 copyPhysReg(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator I, DebugLoc DL,
95 unsigned DestReg, unsigned SrcReg,
97 bool DestCPU = Mips::CPURegsRegClass.contains(DestReg);
98 bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg);
100 // CPU-CPU is the most common.
101 if (DestCPU && SrcCPU) {
102 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
103 .addReg(SrcReg, getKillRegState(KillSrc));
107 // Copy to CPU from other registers.
109 if (Mips::CCRRegClass.contains(SrcReg))
110 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg)
111 .addReg(SrcReg, getKillRegState(KillSrc));
112 else if (Mips::FGR32RegClass.contains(SrcReg))
113 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg)
114 .addReg(SrcReg, getKillRegState(KillSrc));
115 else if (SrcReg == Mips::HI)
116 BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg);
117 else if (SrcReg == Mips::LO)
118 BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg);
120 llvm_unreachable("Copy to CPU from invalid register");
124 // Copy to other registers from CPU.
126 if (Mips::CCRRegClass.contains(DestReg))
127 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg)
128 .addReg(SrcReg, getKillRegState(KillSrc));
129 else if (Mips::FGR32RegClass.contains(DestReg))
130 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg)
131 .addReg(SrcReg, getKillRegState(KillSrc));
132 else if (DestReg == Mips::HI)
133 BuildMI(MBB, I, DL, get(Mips::MTHI))
134 .addReg(SrcReg, getKillRegState(KillSrc));
135 else if (DestReg == Mips::LO)
136 BuildMI(MBB, I, DL, get(Mips::MTLO))
137 .addReg(SrcReg, getKillRegState(KillSrc));
139 llvm_unreachable("Copy from CPU to invalid register");
143 if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) {
144 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg)
145 .addReg(SrcReg, getKillRegState(KillSrc));
149 if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
150 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
151 .addReg(SrcReg, getKillRegState(KillSrc));
155 if (Mips::CCRRegClass.contains(DestReg, SrcReg)) {
156 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg)
157 .addReg(SrcReg, getKillRegState(KillSrc));
160 llvm_unreachable("Cannot copy registers");
164 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
165 unsigned SrcReg, bool isKill, int FI,
166 const TargetRegisterClass *RC,
167 const TargetRegisterInfo *TRI) const {
169 if (I != MBB.end()) DL = I->getDebugLoc();
171 if (RC == Mips::CPURegsRegisterClass)
172 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
173 .addFrameIndex(FI).addImm(0);
174 else if (RC == Mips::FGR32RegisterClass)
175 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
176 .addFrameIndex(FI).addImm(0);
177 else if (RC == Mips::AFGR64RegisterClass) {
178 BuildMI(MBB, I, DL, get(Mips::SDC1))
179 .addReg(SrcReg, getKillRegState(isKill))
180 .addFrameIndex(FI).addImm(0);
182 llvm_unreachable("Register class not handled!");
186 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
187 unsigned DestReg, int FI,
188 const TargetRegisterClass *RC,
189 const TargetRegisterInfo *TRI) const
192 if (I != MBB.end()) DL = I->getDebugLoc();
194 if (RC == Mips::CPURegsRegisterClass)
195 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addFrameIndex(FI).addImm(0);
196 else if (RC == Mips::FGR32RegisterClass)
197 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addFrameIndex(FI).addImm(0);
198 else if (RC == Mips::AFGR64RegisterClass) {
199 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addFrameIndex(FI).addImm(0);
201 llvm_unreachable("Register class not handled!");
205 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
206 uint64_t Offset, const MDNode *MDPtr,
208 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
209 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
213 //===----------------------------------------------------------------------===//
215 //===----------------------------------------------------------------------===//
217 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
218 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
219 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
220 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? Opc : 0;
223 /// GetOppositeBranchOpc - Return the inverse of the specified
224 /// opcode, e.g. turning BEQ to BNE.
225 unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
228 default: llvm_unreachable("Illegal opcode!");
229 case Mips::BEQ : return Mips::BNE;
230 case Mips::BNE : return Mips::BEQ;
231 case Mips::BGTZ : return Mips::BLEZ;
232 case Mips::BGEZ : return Mips::BLTZ;
233 case Mips::BLTZ : return Mips::BGEZ;
234 case Mips::BLEZ : return Mips::BGTZ;
235 case Mips::BC1T : return Mips::BC1F;
236 case Mips::BC1F : return Mips::BC1T;
240 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
241 MachineBasicBlock *&BB,
242 SmallVectorImpl<MachineOperand>& Cond) {
243 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
244 int NumOp = Inst->getNumExplicitOperands();
246 // for both int and fp branches, the last explicit operand is the
248 BB = Inst->getOperand(NumOp-1).getMBB();
249 Cond.push_back(MachineOperand::CreateImm(Opc));
251 for (int i=0; i<NumOp-1; i++)
252 Cond.push_back(Inst->getOperand(i));
255 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
256 MachineBasicBlock *&TBB,
257 MachineBasicBlock *&FBB,
258 SmallVectorImpl<MachineOperand> &Cond,
259 bool AllowModify) const
261 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
263 // Skip all the debug instructions.
264 while (I != REnd && I->isDebugValue())
267 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
268 // If this block ends with no branches (it just falls through to its succ)
269 // just return false, leaving TBB/FBB null.
274 MachineInstr *LastInst = &*I;
275 unsigned LastOpc = LastInst->getOpcode();
277 // Not an analyzable branch (must be an indirect jump).
278 if (!GetAnalyzableBrOpc(LastOpc))
281 // Get the second to last instruction in the block.
282 unsigned SecondLastOpc = 0;
283 MachineInstr *SecondLastInst = NULL;
286 SecondLastInst = &*I;
287 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
289 // Not an analyzable branch (must be an indirect jump).
290 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
294 // If there is only one terminator instruction, process it.
295 if (!SecondLastOpc) {
296 // Unconditional branch
297 if (LastOpc == Mips::J) {
298 TBB = LastInst->getOperand(0).getMBB();
302 // Conditional branch
303 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
307 // If we reached here, there are two branches.
308 // If there are three terminators, we don't know what sort of block this is.
309 if (++I != REnd && isUnpredicatedTerminator(&*I))
312 // If second to last instruction is an unconditional branch,
313 // analyze it and remove the last instruction.
314 if (SecondLastOpc == Mips::J) {
315 // Return if the last instruction cannot be removed.
319 TBB = SecondLastInst->getOperand(0).getMBB();
320 LastInst->eraseFromParent();
324 // Conditional branch followed by an unconditional branch.
325 // The last one must be unconditional.
326 if (LastOpc != Mips::J)
329 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
330 FBB = LastInst->getOperand(0).getMBB();
335 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
336 MachineBasicBlock *TBB, DebugLoc DL,
337 const SmallVectorImpl<MachineOperand>& Cond)
339 unsigned Opc = Cond[0].getImm();
340 const MCInstrDesc &MCID = get(Opc);
341 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
343 for (unsigned i = 1; i < Cond.size(); ++i)
344 MIB.addReg(Cond[i].getReg());
349 unsigned MipsInstrInfo::
350 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
351 MachineBasicBlock *FBB,
352 const SmallVectorImpl<MachineOperand> &Cond,
354 // Shouldn't be a fall through.
355 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
357 // # of condition operands:
358 // Unconditional branches: 0
359 // Floating point branches: 1 (opc)
360 // Int BranchZero: 2 (opc, reg)
361 // Int Branch: 3 (opc, reg0, reg1)
362 assert((Cond.size() <= 3) &&
363 "# of Mips branch conditions must be <= 3!");
365 // Two-way Conditional branch.
367 BuildCondBr(MBB, TBB, DL, Cond);
368 BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
373 // Unconditional branch.
375 BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
376 else // Conditional branch.
377 BuildCondBr(MBB, TBB, DL, Cond);
381 unsigned MipsInstrInfo::
382 RemoveBranch(MachineBasicBlock &MBB) const
384 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
385 MachineBasicBlock::reverse_iterator FirstBr;
388 // Skip all the debug instructions.
389 while (I != REnd && I->isDebugValue())
394 // Up to 2 branches are removed.
395 // Note that indirect branches are not removed.
396 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
397 if (!GetAnalyzableBrOpc(I->getOpcode()))
400 MBB.erase(I.base(), FirstBr.base());
405 /// ReverseBranchCondition - Return the inverse opcode of the
406 /// specified Branch instruction.
408 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
410 assert( (Cond.size() && Cond.size() <= 3) &&
411 "Invalid Mips branch condition!");
412 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
416 /// getGlobalBaseReg - Return a virtual register initialized with the
417 /// the global base register value. Output instructions required to
418 /// initialize the register in the function entry block, if necessary.
420 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
421 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
422 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
423 if (GlobalBaseReg != 0)
424 return GlobalBaseReg;
426 // Insert the set of GlobalBaseReg into the first MBB of the function
427 MachineBasicBlock &FirstMBB = MF->front();
428 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
429 MachineRegisterInfo &RegInfo = MF->getRegInfo();
430 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
432 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
433 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
434 GlobalBaseReg).addReg(Mips::GP);
435 RegInfo.addLiveIn(Mips::GP);
437 MipsFI->setGlobalBaseReg(GlobalBaseReg);
438 return GlobalBaseReg;