1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MipsGenInstrInfo.inc"
25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
39 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
41 // addu $dst, $src, $zero || addu $dst, $zero, $src
42 // or $dst, $src, $zero || or $dst, $zero, $src
43 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44 if (MI.getOperand(1).getReg() == Mips::ZERO) {
45 DstReg = MI.getOperand(0).getReg();
46 SrcReg = MI.getOperand(2).getReg();
48 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(1).getReg();
58 if (MI.getOpcode() == Mips::FMOV_S32 ||
59 MI.getOpcode() == Mips::FMOV_D32 ||
60 MI.getOpcode() == Mips::MFC1 ||
61 MI.getOpcode() == Mips::MTC1 ||
62 MI.getOpcode() == Mips::MOVCCRToCCR) {
63 DstReg = MI.getOperand(0).getReg();
64 SrcReg = MI.getOperand(1).getReg();
68 // addiu $dst, $src, 0
69 if (MI.getOpcode() == Mips::ADDiu) {
70 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71 DstReg = MI.getOperand(0).getReg();
72 SrcReg = MI.getOperand(1).getReg();
80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
81 /// load from a stack slot, return the virtual or physical register number of
82 /// the destination along with the FrameIndex of the loaded stack slot. If
83 /// not, return 0. This predicate must return 0 if the instruction has
84 /// any side effects other than loading from the stack slot.
85 unsigned MipsInstrInfo::
86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
88 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89 (MI->getOpcode() == Mips::LDC1)) {
90 if ((MI->getOperand(2).isFI()) && // is a stack slot
91 (MI->getOperand(1).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(1)))) {
93 FrameIndex = MI->getOperand(2).getIndex();
94 return MI->getOperand(0).getReg();
101 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// store to a stack slot, return the virtual or physical register number of
103 /// the source reg along with the FrameIndex of the loaded stack slot. If
104 /// not, return 0. This predicate must return 0 if the instruction has
105 /// any side effects other than storing to the stack slot.
106 unsigned MipsInstrInfo::
107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
109 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110 (MI->getOpcode() == Mips::SDC1)) {
111 if ((MI->getOperand(2).isFI()) && // is a stack slot
112 (MI->getOperand(1).isImm()) && // the imm is zero
113 (isZeroImm(MI->getOperand(1)))) {
114 FrameIndex = MI->getOperand(2).getIndex();
115 return MI->getOperand(0).getReg();
121 /// insertNoop - If data hazard condition is found insert the target nop
124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
126 DebugLoc DL = DebugLoc::getUnknownLoc();
127 if (MI != MBB.end()) DL = MI->getDebugLoc();
128 BuildMI(MBB, MI, DL, get(Mips::NOP));
132 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
133 unsigned DestReg, unsigned SrcReg,
134 const TargetRegisterClass *DestRC,
135 const TargetRegisterClass *SrcRC) const {
136 DebugLoc DL = DebugLoc::getUnknownLoc();
137 const MachineFunction *MF = MBB.getParent();
138 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
140 if (I != MBB.end()) DL = I->getDebugLoc();
142 if (DestRC != SrcRC) {
144 // Copy to/from FCR31 condition register
145 if ((DestRC == Mips::CPURegsRegisterClass) &&
146 (SrcRC == Mips::CCRRegisterClass))
147 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
148 else if ((DestRC == Mips::CCRRegisterClass) &&
149 (SrcRC == Mips::CPURegsRegisterClass))
150 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
152 // Moves between coprocessors and cpu
153 else if ((DestRC == Mips::CPURegsRegisterClass) &&
154 (SrcRC == Mips::FGR32RegisterClass))
155 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
156 else if ((DestRC == Mips::FGR32RegisterClass) &&
157 (SrcRC == Mips::CPURegsRegisterClass))
158 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
159 else if ((DestRC == Mips::AFGR64RegisterClass) &&
160 (SrcRC == Mips::CPURegsRegisterClass) &&
161 (SrcReg == Mips::ZERO)) {
162 const unsigned *AliasSet = TRI->getAliasSet(DestReg);
163 BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[0]).addReg(SrcReg);
164 BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[1]).addReg(SrcReg);
167 // Move from/to Hi/Lo registers
168 else if ((DestRC == Mips::HILORegisterClass) &&
169 (SrcRC == Mips::CPURegsRegisterClass)) {
170 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
171 BuildMI(MBB, I, DL, get(Opc), DestReg);
172 } else if ((SrcRC == Mips::HILORegisterClass) &&
173 (DestRC == Mips::CPURegsRegisterClass)) {
174 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
175 BuildMI(MBB, I, DL, get(Opc), DestReg);
177 // Can't copy this register
183 if (DestRC == Mips::CPURegsRegisterClass)
184 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
186 else if (DestRC == Mips::FGR32RegisterClass)
187 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
188 else if (DestRC == Mips::AFGR64RegisterClass)
189 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
190 else if (DestRC == Mips::CCRRegisterClass)
191 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
193 // Can't copy this register
200 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
201 unsigned SrcReg, bool isKill, int FI,
202 const TargetRegisterClass *RC) const {
205 DebugLoc DL = DebugLoc::getUnknownLoc();
206 if (I != MBB.end()) DL = I->getDebugLoc();
208 if (RC == Mips::CPURegsRegisterClass)
210 else if (RC == Mips::FGR32RegisterClass)
213 assert(RC == Mips::AFGR64RegisterClass);
217 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
218 .addImm(0).addFrameIndex(FI);
222 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
223 unsigned DestReg, int FI,
224 const TargetRegisterClass *RC) const
227 if (RC == Mips::CPURegsRegisterClass)
229 else if (RC == Mips::FGR32RegisterClass)
232 assert(RC == Mips::AFGR64RegisterClass);
236 DebugLoc DL = DebugLoc::getUnknownLoc();
237 if (I != MBB.end()) DL = I->getDebugLoc();
238 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
241 MachineInstr *MipsInstrInfo::
242 foldMemoryOperandImpl(MachineFunction &MF,
244 const SmallVectorImpl<unsigned> &Ops, int FI) const
246 if (Ops.size() != 1) return NULL;
248 MachineInstr *NewMI = NULL;
250 switch (MI->getOpcode()) {
252 if ((MI->getOperand(0).isReg()) &&
253 (MI->getOperand(1).isReg()) &&
254 (MI->getOperand(1).getReg() == Mips::ZERO) &&
255 (MI->getOperand(2).isReg())) {
256 if (Ops[0] == 0) { // COPY -> STORE
257 unsigned SrcReg = MI->getOperand(2).getReg();
258 bool isKill = MI->getOperand(2).isKill();
259 bool isUndef = MI->getOperand(2).isUndef();
260 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
261 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
262 .addImm(0).addFrameIndex(FI);
263 } else { // COPY -> LOAD
264 unsigned DstReg = MI->getOperand(0).getReg();
265 bool isDead = MI->getOperand(0).isDead();
266 bool isUndef = MI->getOperand(0).isUndef();
267 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
268 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
269 getUndefRegState(isUndef))
270 .addImm(0).addFrameIndex(FI);
276 if ((MI->getOperand(0).isReg()) &&
277 (MI->getOperand(1).isReg())) {
278 const TargetRegisterClass
279 *RC = RI.getRegClass(MI->getOperand(0).getReg());
280 unsigned StoreOpc, LoadOpc;
282 if (RC == Mips::FGR32RegisterClass) {
283 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
285 assert(RC == Mips::AFGR64RegisterClass);
286 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
289 if (Ops[0] == 0) { // COPY -> STORE
290 unsigned SrcReg = MI->getOperand(1).getReg();
291 bool isKill = MI->getOperand(1).isKill();
292 bool isUndef = MI->getOperand(2).isUndef();
293 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
294 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
295 .addImm(0).addFrameIndex(FI) ;
296 } else { // COPY -> LOAD
297 unsigned DstReg = MI->getOperand(0).getReg();
298 bool isDead = MI->getOperand(0).isDead();
299 bool isUndef = MI->getOperand(0).isUndef();
300 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
301 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
302 getUndefRegState(isUndef))
303 .addImm(0).addFrameIndex(FI);
312 //===----------------------------------------------------------------------===//
314 //===----------------------------------------------------------------------===//
316 /// GetCondFromBranchOpc - Return the Mips CC that matches
317 /// the correspondent Branch instruction opcode.
318 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
321 default: return Mips::COND_INVALID;
322 case Mips::BEQ : return Mips::COND_E;
323 case Mips::BNE : return Mips::COND_NE;
324 case Mips::BGTZ : return Mips::COND_GZ;
325 case Mips::BGEZ : return Mips::COND_GEZ;
326 case Mips::BLTZ : return Mips::COND_LZ;
327 case Mips::BLEZ : return Mips::COND_LEZ;
329 // We dont do fp branch analysis yet!
331 case Mips::BC1F : return Mips::COND_INVALID;
335 /// GetCondBranchFromCond - Return the Branch instruction
336 /// opcode that matches the cc.
337 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
340 default: llvm_unreachable("Illegal condition code!");
341 case Mips::COND_E : return Mips::BEQ;
342 case Mips::COND_NE : return Mips::BNE;
343 case Mips::COND_GZ : return Mips::BGTZ;
344 case Mips::COND_GEZ : return Mips::BGEZ;
345 case Mips::COND_LZ : return Mips::BLTZ;
346 case Mips::COND_LEZ : return Mips::BLEZ;
351 case Mips::FCOND_UEQ:
352 case Mips::FCOND_OLT:
353 case Mips::FCOND_ULT:
354 case Mips::FCOND_OLE:
355 case Mips::FCOND_ULE:
357 case Mips::FCOND_NGLE:
358 case Mips::FCOND_SEQ:
359 case Mips::FCOND_NGL:
361 case Mips::FCOND_NGE:
363 case Mips::FCOND_NGT: return Mips::BC1T;
367 case Mips::FCOND_NEQ:
368 case Mips::FCOND_OGL:
369 case Mips::FCOND_UGE:
370 case Mips::FCOND_OGE:
371 case Mips::FCOND_UGT:
372 case Mips::FCOND_OGT:
374 case Mips::FCOND_GLE:
375 case Mips::FCOND_SNE:
377 case Mips::FCOND_NLT:
379 case Mips::FCOND_NLE:
380 case Mips::FCOND_GT: return Mips::BC1F;
384 /// GetOppositeBranchCondition - Return the inverse of the specified
385 /// condition, e.g. turning COND_E to COND_NE.
386 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
389 default: llvm_unreachable("Illegal condition code!");
390 case Mips::COND_E : return Mips::COND_NE;
391 case Mips::COND_NE : return Mips::COND_E;
392 case Mips::COND_GZ : return Mips::COND_LEZ;
393 case Mips::COND_GEZ : return Mips::COND_LZ;
394 case Mips::COND_LZ : return Mips::COND_GEZ;
395 case Mips::COND_LEZ : return Mips::COND_GZ;
396 case Mips::FCOND_F : return Mips::FCOND_T;
397 case Mips::FCOND_UN : return Mips::FCOND_OR;
398 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
399 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
400 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
401 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
402 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
403 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
404 case Mips::FCOND_SF: return Mips::FCOND_ST;
405 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
406 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
407 case Mips::FCOND_NGL: return Mips::FCOND_GL;
408 case Mips::FCOND_LT: return Mips::FCOND_NLT;
409 case Mips::FCOND_NGE: return Mips::FCOND_GE;
410 case Mips::FCOND_LE: return Mips::FCOND_NLE;
411 case Mips::FCOND_NGT: return Mips::FCOND_GT;
415 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
416 MachineBasicBlock *&TBB,
417 MachineBasicBlock *&FBB,
418 SmallVectorImpl<MachineOperand> &Cond,
419 bool AllowModify) const
421 // If the block has no terminators, it just falls into the block after it.
422 MachineBasicBlock::iterator I = MBB.end();
423 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
426 // Get the last instruction in the block.
427 MachineInstr *LastInst = I;
429 // If there is only one terminator instruction, process it.
430 unsigned LastOpc = LastInst->getOpcode();
431 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
432 if (!LastInst->getDesc().isBranch())
435 // Unconditional branch
436 if (LastOpc == Mips::J) {
437 TBB = LastInst->getOperand(0).getMBB();
441 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
442 if (BranchCode == Mips::COND_INVALID)
443 return true; // Can't handle indirect branch.
445 // Conditional branch
446 // Block ends with fall-through condbranch.
447 if (LastOpc != Mips::COND_INVALID) {
448 int LastNumOp = LastInst->getNumOperands();
450 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
451 Cond.push_back(MachineOperand::CreateImm(BranchCode));
453 for (int i=0; i<LastNumOp-1; i++) {
454 Cond.push_back(LastInst->getOperand(i));
461 // Get the instruction before it if it is a terminator.
462 MachineInstr *SecondLastInst = I;
464 // If there are three terminators, we don't know what sort of block this is.
465 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
468 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
469 unsigned SecondLastOpc = SecondLastInst->getOpcode();
470 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
472 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
473 int SecondNumOp = SecondLastInst->getNumOperands();
475 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
476 Cond.push_back(MachineOperand::CreateImm(BranchCode));
478 for (int i=0; i<SecondNumOp-1; i++) {
479 Cond.push_back(SecondLastInst->getOperand(i));
482 FBB = LastInst->getOperand(0).getMBB();
486 // If the block ends with two unconditional branches, handle it. The last
487 // one is not executed, so remove it.
488 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
489 TBB = SecondLastInst->getOperand(0).getMBB();
492 I->eraseFromParent();
496 // Otherwise, can't handle this.
500 unsigned MipsInstrInfo::
501 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
502 MachineBasicBlock *FBB,
503 const SmallVectorImpl<MachineOperand> &Cond) const {
504 // FIXME this should probably have a DebugLoc argument
505 DebugLoc dl = DebugLoc::getUnknownLoc();
506 // Shouldn't be a fall through.
507 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
508 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
509 "Mips branch conditions can have two|three components!");
511 if (FBB == 0) { // One way branch.
513 // Unconditional branch?
514 BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
516 // Conditional branch.
517 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
518 const TargetInstrDesc &TID = get(Opc);
520 if (TID.getNumOperands() == 3)
521 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
522 .addReg(Cond[2].getReg())
525 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
532 // Two-way Conditional branch.
533 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
534 const TargetInstrDesc &TID = get(Opc);
536 if (TID.getNumOperands() == 3)
537 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
540 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
542 BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
546 unsigned MipsInstrInfo::
547 RemoveBranch(MachineBasicBlock &MBB) const
549 MachineBasicBlock::iterator I = MBB.end();
550 if (I == MBB.begin()) return 0;
552 if (I->getOpcode() != Mips::J &&
553 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
556 // Remove the branch.
557 I->eraseFromParent();
561 if (I == MBB.begin()) return 1;
563 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
566 // Remove the branch.
567 I->eraseFromParent();
571 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
572 /// fall-through into its successor block.
574 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
576 if (MBB.empty()) return false;
578 switch (MBB.back().getOpcode()) {
579 case Mips::RET: // Return.
580 case Mips::JR: // Indirect branch.
581 case Mips::J: // Uncond branch.
583 default: return false;
587 /// ReverseBranchCondition - Return the inverse opcode of the
588 /// specified Branch instruction.
590 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
592 assert( (Cond.size() == 3 || Cond.size() == 2) &&
593 "Invalid Mips branch condition!");
594 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
598 /// getGlobalBaseReg - Return a virtual register initialized with the
599 /// the global base register value. Output instructions required to
600 /// initialize the register in the function entry block, if necessary.
602 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
603 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
604 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
605 if (GlobalBaseReg != 0)
606 return GlobalBaseReg;
608 // Insert the set of GlobalBaseReg into the first MBB of the function
609 MachineBasicBlock &FirstMBB = MF->front();
610 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
611 MachineRegisterInfo &RegInfo = MF->getRegInfo();
612 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
614 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
615 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
616 Mips::CPURegsRegisterClass,
617 Mips::CPURegsRegisterClass);
618 assert(Ok && "Couldn't assign to global base register!");
619 Ok = Ok; // Silence warning when assertions are turned off.
620 RegInfo.addLiveIn(Mips::GP);
622 MipsFI->setGlobalBaseReg(GlobalBaseReg);
623 return GlobalBaseReg;