lib/Target/Mips/MipsInstrInfo.h

   1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef MIPSINSTRUCTIONINFO_H
  15 #define MIPSINSTRUCTIONINFO_H
  16
  17 #include "Mips.h"
  18 #include "MipsAnalyzeImmediate.h"
  19 #include "MipsRegisterInfo.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Target/TargetInstrInfo.h"
  23
  24 #define GET_INSTRINFO_HEADER
  25 #include "MipsGenInstrInfo.inc"
  26
  27 namespace llvm {
  28
  29 class MipsInstrInfo : public MipsGenInstrInfo {
  30 protected:
  31   MipsTargetMachine &TM;
  32   unsigned UncondBrOpc;
  33
  34 public:
  35   enum BranchType {
  36     BT_None,       // Couldn't analyze branch.
  37     BT_NoBranch,   // No branches found.
  38     BT_Uncond,     // One unconditional branch.
  39     BT_Cond,       // One conditional branch.
  40     BT_CondUncond, // A conditional branch followed by an unconditional branch.
  41     BT_Indirect    // One indirct branch.
  42   };
  43
  44   explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc);
  45
  46   static const MipsInstrInfo *create(MipsTargetMachine &TM);
  47
  48   /// Branch Analysis
  49   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  50                              MachineBasicBlock *&FBB,
  51                              SmallVectorImpl<MachineOperand> &Cond,
  52                              bool AllowModify) const;
  53
  54   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  55
  56   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  57                                 MachineBasicBlock *FBB,
  58                                 const SmallVectorImpl<MachineOperand> &Cond,
  59                                 DebugLoc DL) const;
  60
  61   virtual
  62   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  63
  64   BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  65                            MachineBasicBlock *&FBB,
  66                            SmallVectorImpl<MachineOperand> &Cond,
  67                            bool AllowModify,
  68                            SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
  69
  70   virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
  71                                                  int FrameIx, uint64_t Offset,
  72                                                  const MDNode *MDPtr,
  73                                                  DebugLoc DL) const;
  74
  75   /// Insert nop instruction when hazard condition is found
  76   virtual void insertNoop(MachineBasicBlock &MBB,
  77                           MachineBasicBlock::iterator MI) const;
  78
  79   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  80   /// such, whenever a client has an instance of instruction info, it should
  81   /// always be able to get register info as well (through this method).
  82   ///
  83   virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
  84
  85   virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
  86
  87   /// Return the number of bytes of code the specified instruction may be.
  88   unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
  89
  90   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  91                                    MachineBasicBlock::iterator MBBI,
  92                                    unsigned SrcReg, bool isKill, int FrameIndex,
  93                                    const TargetRegisterClass *RC,
  94                                    const TargetRegisterInfo *TRI) const {
  95     storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
  96   }
  97
  98   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  99                                     MachineBasicBlock::iterator MBBI,
 100                                     unsigned DestReg, int FrameIndex,
 101                                     const TargetRegisterClass *RC,
 102                                     const TargetRegisterInfo *TRI) const {
 103     loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
 104   }
 105
 106   virtual void storeRegToStack(MachineBasicBlock &MBB,
 107                                MachineBasicBlock::iterator MI,
 108                                unsigned SrcReg, bool isKill, int FrameIndex,
 109                                const TargetRegisterClass *RC,
 110                                const TargetRegisterInfo *TRI,
 111                                int64_t Offset) const = 0;
 112
 113   virtual void loadRegFromStack(MachineBasicBlock &MBB,
 114                                 MachineBasicBlock::iterator MI,
 115                                 unsigned DestReg, int FrameIndex,
 116                                 const TargetRegisterClass *RC,
 117                                 const TargetRegisterInfo *TRI,
 118                                 int64_t Offset) const = 0;
 119
 120   /// Create an instruction which has the same operands and memory operands
 121   /// as MI but has a new opcode.
 122   MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
 123                                          MachineBasicBlock::iterator I) const;
 124
 125 protected:
 126   bool isZeroImm(const MachineOperand &op) const;
 127
 128   MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
 129                                    unsigned Flag) const;
 130
 131 private:
 132   virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
 133
 134   void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
 135                      MachineBasicBlock *&BB,
 136                      SmallVectorImpl<MachineOperand> &Cond) const;
 137
 138   void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
 139                    const SmallVectorImpl<MachineOperand>& Cond) const;
 140 };
 141
 142 /// Create MipsInstrInfo objects.
 143 const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM);
 144 const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);
 145
 146 }
 147
 148 #endif