1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "MipsRegisterInfo.h"
34 // Mips Condition Codes
36 // To be used with float branch True
54 // To be used with float branch False
55 // This conditions have the same mnemonic as the
56 // above ones, but are used with a branch False;
74 // Only integer conditions
84 // Turn condition code into conditional branch opcode.
85 unsigned GetCondBranchFromCond(CondCode CC);
87 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
88 /// e.g. turning COND_E to COND_NE.
89 CondCode GetOppositeBranchCondition(Mips::CondCode CC);
91 /// MipsCCToString - Map each FP condition code to its string
92 inline static const char *MipsFCCToString(Mips::CondCode CC)
95 default: assert(0 && "Unknown condition code");
97 case FCOND_T: return "f";
99 case FCOND_OR: return "un";
101 case FCOND_NEQ: return "eq";
103 case FCOND_OGL: return "ueq";
105 case FCOND_UGE: return "olt";
107 case FCOND_OGE: return "ult";
109 case FCOND_UGT: return "ole";
111 case FCOND_OGT: return "ule";
113 case FCOND_ST: return "sf";
115 case FCOND_GLE: return "ngle";
117 case FCOND_SNE: return "seq";
119 case FCOND_GL: return "ngl";
121 case FCOND_NLT: return "lt";
123 case FCOND_GE: return "ge";
125 case FCOND_NLE: return "nle";
127 case FCOND_GT: return "gt";
132 class MipsInstrInfo : public TargetInstrInfoImpl {
133 MipsTargetMachine &TM;
134 const MipsRegisterInfo RI;
136 explicit MipsInstrInfo(MipsTargetMachine &TM);
138 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
139 /// such, whenever a client has an instance of instruction info, it should
140 /// always be able to get register info as well (through this method).
142 virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
144 /// Return true if the instruction is a register to register move and return
145 /// the source and dest operands and their sub-register indices by reference.
146 virtual bool isMoveInstr(const MachineInstr &MI,
147 unsigned &SrcReg, unsigned &DstReg,
148 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
150 /// isLoadFromStackSlot - If the specified machine instruction is a direct
151 /// load from a stack slot, return the virtual or physical register number of
152 /// the destination along with the FrameIndex of the loaded stack slot. If
153 /// not, return 0. This predicate must return 0 if the instruction has
154 /// any side effects other than loading from the stack slot.
155 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
156 int &FrameIndex) const;
158 /// isStoreToStackSlot - If the specified machine instruction is a direct
159 /// store to a stack slot, return the virtual or physical register number of
160 /// the source reg along with the FrameIndex of the loaded stack slot. If
161 /// not, return 0. This predicate must return 0 if the instruction has
162 /// any side effects other than storing to the stack slot.
163 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
164 int &FrameIndex) const;
167 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
168 MachineBasicBlock *&FBB,
169 SmallVectorImpl<MachineOperand> &Cond,
170 bool AllowModify) const;
171 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
172 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
173 MachineBasicBlock *FBB,
174 const SmallVectorImpl<MachineOperand> &Cond) const;
175 virtual bool copyRegToReg(MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator I,
177 unsigned DestReg, unsigned SrcReg,
178 const TargetRegisterClass *DestRC,
179 const TargetRegisterClass *SrcRC) const;
180 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator MBBI,
182 unsigned SrcReg, bool isKill, int FrameIndex,
183 const TargetRegisterClass *RC) const;
185 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
186 SmallVectorImpl<MachineOperand> &Addr,
187 const TargetRegisterClass *RC,
188 SmallVectorImpl<MachineInstr*> &NewMIs) const;
190 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator MBBI,
192 unsigned DestReg, int FrameIndex,
193 const TargetRegisterClass *RC) const;
195 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
196 SmallVectorImpl<MachineOperand> &Addr,
197 const TargetRegisterClass *RC,
198 SmallVectorImpl<MachineInstr*> &NewMIs) const;
200 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
202 const SmallVectorImpl<unsigned> &Ops,
203 int FrameIndex) const;
205 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
207 const SmallVectorImpl<unsigned> &Ops,
208 MachineInstr* LoadMI) const {
212 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
214 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
216 /// Insert nop instruction when hazard condition is found
217 virtual void insertNoop(MachineBasicBlock &MBB,
218 MachineBasicBlock::iterator MI) const;