1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "MipsGenInstrInfo.inc"
28 class MipsInstrInfo : public MipsGenInstrInfo {
29 MipsTargetMachine &TM;
30 bool IsN64; bool InMips16Mode;
31 const MipsRegisterInfo RI;
34 explicit MipsInstrInfo(MipsTargetMachine &TM);
36 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
37 /// such, whenever a client has an instance of instruction info, it should
38 /// always be able to get register info as well (through this method).
40 virtual const MipsRegisterInfo &getRegisterInfo() const;
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const;
50 /// isStoreToStackSlot - If the specified machine instruction is a direct
51 /// store to a stack slot, return the virtual or physical register number of
52 /// the source reg along with the FrameIndex of the loaded stack slot. If
53 /// not, return 0. This predicate must return 0 if the instruction has
54 /// any side effects other than storing to the stack slot.
55 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
56 int &FrameIndex) const;
59 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
60 MachineBasicBlock *&FBB,
61 SmallVectorImpl<MachineOperand> &Cond,
62 bool AllowModify) const;
63 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66 void ExpandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
68 void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
71 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
72 const SmallVectorImpl<MachineOperand>& Cond) const;
73 void ExpandExtractElementF64(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator I) const;
75 void ExpandBuildPairF64(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator I) const;
79 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
80 MachineBasicBlock *FBB,
81 const SmallVectorImpl<MachineOperand> &Cond,
83 virtual void copyPhysReg(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI, DebugLoc DL,
85 unsigned DestReg, unsigned SrcReg,
87 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MBBI,
89 unsigned SrcReg, bool isKill, int FrameIndex,
90 const TargetRegisterClass *RC,
91 const TargetRegisterInfo *TRI) const;
93 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator MBBI,
95 unsigned DestReg, int FrameIndex,
96 const TargetRegisterClass *RC,
97 const TargetRegisterInfo *TRI) const;
99 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
101 virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
102 int FrameIx, uint64_t Offset,
107 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
109 /// Insert nop instruction when hazard condition is found
110 virtual void insertNoop(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MI) const;
113 /// Return the number of bytes of code the specified instruction may be.
114 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
118 /// GetOppositeBranchOpc - Return the inverse of the specified
119 /// opcode, e.g. turning BEQ to BNE.
120 unsigned GetOppositeBranchOpc(unsigned Opc);
122 /// Emit a series of instructions to load an immediate. All instructions
123 /// except for the last one are emitted. The function returns the number of
124 /// MachineInstrs generated. The opcode-immediate pair of the last
125 /// instruction is returned in LastInst, if it is not 0.
127 loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
128 MachineBasicBlock& MBB, MachineBasicBlock::iterator II,
129 DebugLoc DL, bool LastInstrIsADDiu,
130 MipsAnalyzeImmediate::Inst *LastInst);