1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "MipsRegisterInfo.h"
35 // Mips Condition Codes
37 // To be used with float branch True
55 // To be used with float branch False
56 // This conditions have the same mnemonic as the
57 // above ones, but are used with a branch False;
75 // Only integer conditions
85 // Turn condition code into conditional branch opcode.
86 unsigned GetCondBranchFromCond(CondCode CC);
88 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
89 /// e.g. turning COND_E to COND_NE.
90 CondCode GetOppositeBranchCondition(Mips::CondCode CC);
92 /// MipsCCToString - Map each FP condition code to its string
93 inline static const char *MipsFCCToString(Mips::CondCode CC)
96 default: llvm_unreachable("Unknown condition code");
98 case FCOND_T: return "f";
100 case FCOND_OR: return "un";
102 case FCOND_NEQ: return "eq";
104 case FCOND_OGL: return "ueq";
106 case FCOND_UGE: return "olt";
108 case FCOND_OGE: return "ult";
110 case FCOND_UGT: return "ole";
112 case FCOND_OGT: return "ule";
114 case FCOND_ST: return "sf";
116 case FCOND_GLE: return "ngle";
118 case FCOND_SNE: return "seq";
120 case FCOND_GL: return "ngl";
122 case FCOND_NLT: return "lt";
124 case FCOND_GE: return "ge";
126 case FCOND_NLE: return "nle";
128 case FCOND_GT: return "gt";
133 /// MipsII - This namespace holds all of the target specific flags that
134 /// instruction info tracks.
137 /// Target Operand Flag enum.
139 //===------------------------------------------------------------------===//
140 // Mips Specific MachineOperand flags.
144 /// MO_GOT - Represents the offset into the global offset table at which
145 /// the address the relocation entry symbol resides during execution.
148 /// MO_GOT_CALL - Represents the offset into the global offset table at
149 /// which the address of a call site relocation entry symbol resides
150 /// during execution. This is different from the above since this flag
151 /// can only be present in call instructions.
154 /// MO_GPREL - Represents the offset from the current gp value to be used
155 /// for the relocatable object file being produced.
158 /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
165 class MipsInstrInfo : public TargetInstrInfoImpl {
166 MipsTargetMachine &TM;
167 const MipsRegisterInfo RI;
169 explicit MipsInstrInfo(MipsTargetMachine &TM);
171 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
172 /// such, whenever a client has an instance of instruction info, it should
173 /// always be able to get register info as well (through this method).
175 virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
177 /// isLoadFromStackSlot - If the specified machine instruction is a direct
178 /// load from a stack slot, return the virtual or physical register number of
179 /// the destination along with the FrameIndex of the loaded stack slot. If
180 /// not, return 0. This predicate must return 0 if the instruction has
181 /// any side effects other than loading from the stack slot.
182 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
183 int &FrameIndex) const;
185 /// isStoreToStackSlot - If the specified machine instruction is a direct
186 /// store to a stack slot, return the virtual or physical register number of
187 /// the source reg along with the FrameIndex of the loaded stack slot. If
188 /// not, return 0. This predicate must return 0 if the instruction has
189 /// any side effects other than storing to the stack slot.
190 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
191 int &FrameIndex) const;
194 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
195 MachineBasicBlock *&FBB,
196 SmallVectorImpl<MachineOperand> &Cond,
197 bool AllowModify) const;
198 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
199 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
200 MachineBasicBlock *FBB,
201 const SmallVectorImpl<MachineOperand> &Cond,
203 virtual void copyPhysReg(MachineBasicBlock &MBB,
204 MachineBasicBlock::iterator MI, DebugLoc DL,
205 unsigned DestReg, unsigned SrcReg,
207 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
208 MachineBasicBlock::iterator MBBI,
209 unsigned SrcReg, bool isKill, int FrameIndex,
210 const TargetRegisterClass *RC,
211 const TargetRegisterInfo *TRI) const;
213 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
214 MachineBasicBlock::iterator MBBI,
215 unsigned DestReg, int FrameIndex,
216 const TargetRegisterClass *RC,
217 const TargetRegisterInfo *TRI) const;
220 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
222 /// Insert nop instruction when hazard condition is found
223 virtual void insertNoop(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator MI) const;
226 /// getGlobalBaseReg - Return a virtual register initialized with the
227 /// the global base register value. Output instructions required to
228 /// initialize the register in the function entry block, if necessary.
230 unsigned getGlobalBaseReg(MachineFunction *MF) const;