1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "MipsRegisterInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "MipsGenInstrInfo.inc"
28 /// GetOppositeBranchOpc - Return the inverse of the specified
29 /// opcode, e.g. turning BEQ to BNE.
30 unsigned GetOppositeBranchOpc(unsigned Opc);
33 class MipsInstrInfo : public MipsGenInstrInfo {
34 MipsTargetMachine &TM;
36 const MipsRegisterInfo RI;
39 explicit MipsInstrInfo(MipsTargetMachine &TM);
41 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
42 /// such, whenever a client has an instance of instruction info, it should
43 /// always be able to get register info as well (through this method).
45 virtual const MipsRegisterInfo &getRegisterInfo() const;
47 /// isLoadFromStackSlot - If the specified machine instruction is a direct
48 /// load from a stack slot, return the virtual or physical register number of
49 /// the destination along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than loading from the stack slot.
52 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const;
55 /// isStoreToStackSlot - If the specified machine instruction is a direct
56 /// store to a stack slot, return the virtual or physical register number of
57 /// the source reg along with the FrameIndex of the loaded stack slot. If
58 /// not, return 0. This predicate must return 0 if the instruction has
59 /// any side effects other than storing to the stack slot.
60 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
61 int &FrameIndex) const;
64 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
65 MachineBasicBlock *&FBB,
66 SmallVectorImpl<MachineOperand> &Cond,
67 bool AllowModify) const;
68 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
71 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
72 const SmallVectorImpl<MachineOperand>& Cond) const;
75 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
76 MachineBasicBlock *FBB,
77 const SmallVectorImpl<MachineOperand> &Cond,
79 virtual void copyPhysReg(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MI, DebugLoc DL,
81 unsigned DestReg, unsigned SrcReg,
83 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MBBI,
85 unsigned SrcReg, bool isKill, int FrameIndex,
86 const TargetRegisterClass *RC,
87 const TargetRegisterInfo *TRI) const;
89 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MBBI,
91 unsigned DestReg, int FrameIndex,
92 const TargetRegisterClass *RC,
93 const TargetRegisterInfo *TRI) const;
95 virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
96 int FrameIx, uint64_t Offset,
101 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
103 /// Insert nop instruction when hazard condition is found
104 virtual void insertNoop(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MI) const;