1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "MipsRegisterInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "MipsGenInstrInfo.inc"
28 /// GetOppositeBranchOpc - Return the inverse of the specified
29 /// opcode, e.g. turning BEQ to BNE.
30 unsigned GetOppositeBranchOpc(unsigned Opc);
33 class MipsInstrInfo : public MipsGenInstrInfo {
34 MipsTargetMachine &TM;
36 const MipsRegisterInfo RI;
38 explicit MipsInstrInfo(MipsTargetMachine &TM);
40 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
41 /// such, whenever a client has an instance of instruction info, it should
42 /// always be able to get register info as well (through this method).
44 virtual const MipsRegisterInfo &getRegisterInfo() const;
46 /// isLoadFromStackSlot - If the specified machine instruction is a direct
47 /// load from a stack slot, return the virtual or physical register number of
48 /// the destination along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than loading from the stack slot.
51 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
52 int &FrameIndex) const;
54 /// isStoreToStackSlot - If the specified machine instruction is a direct
55 /// store to a stack slot, return the virtual or physical register number of
56 /// the source reg along with the FrameIndex of the loaded stack slot. If
57 /// not, return 0. This predicate must return 0 if the instruction has
58 /// any side effects other than storing to the stack slot.
59 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
60 int &FrameIndex) const;
63 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
64 MachineBasicBlock *&FBB,
65 SmallVectorImpl<MachineOperand> &Cond,
66 bool AllowModify) const;
67 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
70 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
71 const SmallVectorImpl<MachineOperand>& Cond) const;
74 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
75 MachineBasicBlock *FBB,
76 const SmallVectorImpl<MachineOperand> &Cond,
78 virtual void copyPhysReg(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI, DebugLoc DL,
80 unsigned DestReg, unsigned SrcReg,
82 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MBBI,
84 unsigned SrcReg, bool isKill, int FrameIndex,
85 const TargetRegisterClass *RC,
86 const TargetRegisterInfo *TRI) const;
88 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MBBI,
90 unsigned DestReg, int FrameIndex,
91 const TargetRegisterClass *RC,
92 const TargetRegisterInfo *TRI) const;
94 virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
95 int FrameIx, uint64_t Offset,
100 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
102 /// Insert nop instruction when hazard condition is found
103 virtual void insertNoop(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator MI) const;
106 /// getGlobalBaseReg - Return a virtual register initialized with the
107 /// the global base register value. Output instructions required to
108 /// initialize the register in the function entry block, if necessary.
110 unsigned getGlobalBaseReg(MachineFunction *MF) const;