1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #include "MipsGenInstrInfo.inc"
29 class MipsInstrInfo : public MipsGenInstrInfo {
31 MipsTargetMachine &TM;
36 BT_None, // Couldn't analyze branch.
37 BT_NoBranch, // No branches found.
38 BT_Uncond, // One unconditional branch.
39 BT_Cond, // One conditional branch.
40 BT_CondUncond, // A conditional branch followed by an unconditional branch.
41 BT_Indirect // One indirct branch.
44 explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc);
46 static const MipsInstrInfo *create(MipsTargetMachine &TM);
49 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
50 MachineBasicBlock *&FBB,
51 SmallVectorImpl<MachineOperand> &Cond,
52 bool AllowModify) const;
54 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
56 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
57 MachineBasicBlock *FBB,
58 const SmallVectorImpl<MachineOperand> &Cond,
62 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
64 BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
65 MachineBasicBlock *&FBB,
66 SmallVectorImpl<MachineOperand> &Cond,
68 SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
70 /// Insert nop instruction when hazard condition is found
71 virtual void insertNoop(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MI) const;
74 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
75 /// such, whenever a client has an instance of instruction info, it should
76 /// always be able to get register info as well (through this method).
78 virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
80 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
82 /// Return the number of bytes of code the specified instruction may be.
83 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
85 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI,
87 unsigned SrcReg, bool isKill, int FrameIndex,
88 const TargetRegisterClass *RC,
89 const TargetRegisterInfo *TRI) const {
90 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
93 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator MBBI,
95 unsigned DestReg, int FrameIndex,
96 const TargetRegisterClass *RC,
97 const TargetRegisterInfo *TRI) const {
98 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
101 virtual void storeRegToStack(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MI,
103 unsigned SrcReg, bool isKill, int FrameIndex,
104 const TargetRegisterClass *RC,
105 const TargetRegisterInfo *TRI,
106 int64_t Offset) const = 0;
108 virtual void loadRegFromStack(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MI,
110 unsigned DestReg, int FrameIndex,
111 const TargetRegisterClass *RC,
112 const TargetRegisterInfo *TRI,
113 int64_t Offset) const = 0;
115 /// Create an instruction which has the same operands and memory operands
116 /// as MI but has a new opcode.
117 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
118 MachineBasicBlock::iterator I) const;
121 bool isZeroImm(const MachineOperand &op) const;
123 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
124 unsigned Flag) const;
127 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
129 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
130 MachineBasicBlock *&BB,
131 SmallVectorImpl<MachineOperand> &Cond) const;
133 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
134 const SmallVectorImpl<MachineOperand>& Cond) const;
137 /// Create MipsInstrInfo objects.
138 const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM);
139 const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);