1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "MipsRegisterInfo.h"
35 // Mips Condition Codes
37 // To be used with float branch True
55 // To be used with float branch False
56 // This conditions have the same mnemonic as the
57 // above ones, but are used with a branch False;
75 // Only integer conditions
85 // Turn condition code into conditional branch opcode.
86 unsigned GetCondBranchFromCond(CondCode CC);
88 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
89 /// e.g. turning COND_E to COND_NE.
90 CondCode GetOppositeBranchCondition(Mips::CondCode CC);
92 /// MipsCCToString - Map each FP condition code to its string
93 inline static const char *MipsFCCToString(Mips::CondCode CC)
96 default: llvm_unreachable("Unknown condition code");
98 case FCOND_T: return "f";
100 case FCOND_OR: return "un";
102 case FCOND_NEQ: return "eq";
104 case FCOND_OGL: return "ueq";
106 case FCOND_UGE: return "olt";
108 case FCOND_OGE: return "ult";
110 case FCOND_UGT: return "ole";
112 case FCOND_OGT: return "ule";
114 case FCOND_ST: return "sf";
116 case FCOND_GLE: return "ngle";
118 case FCOND_SNE: return "seq";
120 case FCOND_GL: return "ngl";
122 case FCOND_NLT: return "lt";
124 case FCOND_GE: return "ge";
126 case FCOND_NLE: return "nle";
128 case FCOND_GT: return "gt";
133 class MipsInstrInfo : public TargetInstrInfoImpl {
134 MipsTargetMachine &TM;
135 const MipsRegisterInfo RI;
137 explicit MipsInstrInfo(MipsTargetMachine &TM);
139 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
140 /// such, whenever a client has an instance of instruction info, it should
141 /// always be able to get register info as well (through this method).
143 virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
145 /// Return true if the instruction is a register to register move and return
146 /// the source and dest operands and their sub-register indices by reference.
147 virtual bool isMoveInstr(const MachineInstr &MI,
148 unsigned &SrcReg, unsigned &DstReg,
149 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
151 /// isLoadFromStackSlot - If the specified machine instruction is a direct
152 /// load from a stack slot, return the virtual or physical register number of
153 /// the destination along with the FrameIndex of the loaded stack slot. If
154 /// not, return 0. This predicate must return 0 if the instruction has
155 /// any side effects other than loading from the stack slot.
156 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
157 int &FrameIndex) const;
159 /// isStoreToStackSlot - If the specified machine instruction is a direct
160 /// store to a stack slot, return the virtual or physical register number of
161 /// the source reg along with the FrameIndex of the loaded stack slot. If
162 /// not, return 0. This predicate must return 0 if the instruction has
163 /// any side effects other than storing to the stack slot.
164 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
165 int &FrameIndex) const;
168 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
169 MachineBasicBlock *&FBB,
170 SmallVectorImpl<MachineOperand> &Cond,
171 bool AllowModify) const;
172 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
173 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
174 MachineBasicBlock *FBB,
175 const SmallVectorImpl<MachineOperand> &Cond) const;
176 virtual bool copyRegToReg(MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator I,
178 unsigned DestReg, unsigned SrcReg,
179 const TargetRegisterClass *DestRC,
180 const TargetRegisterClass *SrcRC) const;
181 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator MBBI,
183 unsigned SrcReg, bool isKill, int FrameIndex,
184 const TargetRegisterClass *RC) const;
186 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
187 MachineBasicBlock::iterator MBBI,
188 unsigned DestReg, int FrameIndex,
189 const TargetRegisterClass *RC) const;
191 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
193 const SmallVectorImpl<unsigned> &Ops,
194 int FrameIndex) const;
196 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
198 const SmallVectorImpl<unsigned> &Ops,
199 MachineInstr* LoadMI) const {
203 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
205 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
207 /// Insert nop instruction when hazard condition is found
208 virtual void insertNoop(MachineBasicBlock &MBB,
209 MachineBasicBlock::iterator MI) const;
211 /// getGlobalBaseReg - Return a virtual register initialized with the
212 /// the global base register value. Output instructions required to
213 /// initialize the register in the function entry block, if necessary.
215 unsigned getGlobalBaseReg(MachineFunction *MF) const;