1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "MipsRegisterInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "MipsGenInstrInfo.inc"
28 /// GetOppositeBranchOpc - Return the inverse of the specified
29 /// opcode, e.g. turning BEQ to BNE.
30 unsigned GetOppositeBranchOpc(unsigned Opc);
33 /// MipsII - This namespace holds all of the target specific flags that
34 /// instruction info tracks.
37 /// Target Operand Flag enum.
39 //===------------------------------------------------------------------===//
40 // Mips Specific MachineOperand flags.
44 /// MO_GOT - Represents the offset into the global offset table at which
45 /// the address the relocation entry symbol resides during execution.
48 /// MO_GOT_CALL - Represents the offset into the global offset table at
49 /// which the address of a call site relocation entry symbol resides
50 /// during execution. This is different from the above since this flag
51 /// can only be present in call instructions.
54 /// MO_GPREL - Represents the offset from the current gp value to be used
55 /// for the relocatable object file being produced.
58 /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
63 /// MO_TLSGD - Represents the offset into the global offset table at which
64 // the module ID and TSL block offset reside during execution (General
68 /// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
72 /// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
73 // the thread pointer (Local Exec TLS).
86 //===------------------------------------------------------------------===//
87 // Instruction encodings. These are the standard/most common forms for
91 // Pseudo - This represents an instruction that is a pseudo instruction
92 // or one that has not been implemented yet. It is illegal to code generate
93 // it, but tolerated for intermediate implementation stages.
96 /// FrmR - This form is for instructions of the format R.
98 /// FrmI - This form is for instructions of the format I.
100 /// FrmJ - This form is for instructions of the format J.
102 /// FrmFR - This form is for instructions of the format FR.
104 /// FrmFI - This form is for instructions of the format FI.
106 /// FrmOther - This form is for instructions that have no specific format.
113 class MipsInstrInfo : public MipsGenInstrInfo {
114 MipsTargetMachine &TM;
116 const MipsRegisterInfo RI;
118 explicit MipsInstrInfo(MipsTargetMachine &TM);
120 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
121 /// such, whenever a client has an instance of instruction info, it should
122 /// always be able to get register info as well (through this method).
124 virtual const MipsRegisterInfo &getRegisterInfo() const;
126 /// isLoadFromStackSlot - If the specified machine instruction is a direct
127 /// load from a stack slot, return the virtual or physical register number of
128 /// the destination along with the FrameIndex of the loaded stack slot. If
129 /// not, return 0. This predicate must return 0 if the instruction has
130 /// any side effects other than loading from the stack slot.
131 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
132 int &FrameIndex) const;
134 /// isStoreToStackSlot - If the specified machine instruction is a direct
135 /// store to a stack slot, return the virtual or physical register number of
136 /// the source reg along with the FrameIndex of the loaded stack slot. If
137 /// not, return 0. This predicate must return 0 if the instruction has
138 /// any side effects other than storing to the stack slot.
139 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
140 int &FrameIndex) const;
143 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
144 MachineBasicBlock *&FBB,
145 SmallVectorImpl<MachineOperand> &Cond,
146 bool AllowModify) const;
147 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
150 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
151 const SmallVectorImpl<MachineOperand>& Cond) const;
154 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
155 MachineBasicBlock *FBB,
156 const SmallVectorImpl<MachineOperand> &Cond,
158 virtual void copyPhysReg(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator MI, DebugLoc DL,
160 unsigned DestReg, unsigned SrcReg,
162 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MBBI,
164 unsigned SrcReg, bool isKill, int FrameIndex,
165 const TargetRegisterClass *RC,
166 const TargetRegisterInfo *TRI) const;
168 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
169 MachineBasicBlock::iterator MBBI,
170 unsigned DestReg, int FrameIndex,
171 const TargetRegisterClass *RC,
172 const TargetRegisterInfo *TRI) const;
174 virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
175 int FrameIx, uint64_t Offset,
180 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
182 /// Insert nop instruction when hazard condition is found
183 virtual void insertNoop(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MI) const;
186 /// getGlobalBaseReg - Return a virtual register initialized with the
187 /// the global base register value. Output instructions required to
188 /// initialize the register in the function entry block, if necessary.
190 unsigned getGlobalBaseReg(MachineFunction *MF) const;