1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "MipsRegisterInfo.h"
35 // Mips Condition Codes
37 // To be used with float branch True
55 // To be used with float branch False
56 // This conditions have the same mnemonic as the
57 // above ones, but are used with a branch False;
76 /// GetOppositeBranchOpc - Return the inverse of the specified
77 /// opcode, e.g. turning BEQ to BNE.
78 unsigned GetOppositeBranchOpc(unsigned Opc);
80 /// MipsCCToString - Map each FP condition code to its string
81 inline static const char *MipsFCCToString(Mips::CondCode CC)
84 default: llvm_unreachable("Unknown condition code");
86 case FCOND_T: return "f";
88 case FCOND_OR: return "un";
90 case FCOND_UNE: return "eq";
92 case FCOND_ONE: return "ueq";
94 case FCOND_UGE: return "olt";
96 case FCOND_OGE: return "ult";
98 case FCOND_UGT: return "ole";
100 case FCOND_OGT: return "ule";
102 case FCOND_ST: return "sf";
104 case FCOND_GLE: return "ngle";
106 case FCOND_SNE: return "seq";
108 case FCOND_GL: return "ngl";
110 case FCOND_NLT: return "lt";
112 case FCOND_GE: return "nge";
114 case FCOND_NLE: return "le";
116 case FCOND_GT: return "ngt";
121 /// MipsII - This namespace holds all of the target specific flags that
122 /// instruction info tracks.
125 /// Target Operand Flag enum.
127 //===------------------------------------------------------------------===//
128 // Mips Specific MachineOperand flags.
132 /// MO_GOT - Represents the offset into the global offset table at which
133 /// the address the relocation entry symbol resides during execution.
136 /// MO_GOT_CALL - Represents the offset into the global offset table at
137 /// which the address of a call site relocation entry symbol resides
138 /// during execution. This is different from the above since this flag
139 /// can only be present in call instructions.
142 /// MO_GPREL - Represents the offset from the current gp value to be used
143 /// for the relocatable object file being produced.
146 /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
153 class MipsInstrInfo : public TargetInstrInfoImpl {
154 MipsTargetMachine &TM;
155 const MipsRegisterInfo RI;
157 explicit MipsInstrInfo(MipsTargetMachine &TM);
159 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
160 /// such, whenever a client has an instance of instruction info, it should
161 /// always be able to get register info as well (through this method).
163 virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
165 /// isLoadFromStackSlot - If the specified machine instruction is a direct
166 /// load from a stack slot, return the virtual or physical register number of
167 /// the destination along with the FrameIndex of the loaded stack slot. If
168 /// not, return 0. This predicate must return 0 if the instruction has
169 /// any side effects other than loading from the stack slot.
170 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
171 int &FrameIndex) const;
173 /// isStoreToStackSlot - If the specified machine instruction is a direct
174 /// store to a stack slot, return the virtual or physical register number of
175 /// the source reg along with the FrameIndex of the loaded stack slot. If
176 /// not, return 0. This predicate must return 0 if the instruction has
177 /// any side effects other than storing to the stack slot.
178 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
179 int &FrameIndex) const;
182 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
183 MachineBasicBlock *&FBB,
184 SmallVectorImpl<MachineOperand> &Cond,
185 bool AllowModify) const;
186 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
189 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
190 const SmallVectorImpl<MachineOperand>& Cond) const;
193 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
194 MachineBasicBlock *FBB,
195 const SmallVectorImpl<MachineOperand> &Cond,
197 virtual void copyPhysReg(MachineBasicBlock &MBB,
198 MachineBasicBlock::iterator MI, DebugLoc DL,
199 unsigned DestReg, unsigned SrcReg,
201 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MBBI,
203 unsigned SrcReg, bool isKill, int FrameIndex,
204 const TargetRegisterClass *RC,
205 const TargetRegisterInfo *TRI) const;
207 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
208 MachineBasicBlock::iterator MBBI,
209 unsigned DestReg, int FrameIndex,
210 const TargetRegisterClass *RC,
211 const TargetRegisterInfo *TRI) const;
214 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
216 /// Insert nop instruction when hazard condition is found
217 virtual void insertNoop(MachineBasicBlock &MBB,
218 MachineBasicBlock::iterator MI) const;
220 /// getGlobalBaseReg - Return a virtual register initialized with the
221 /// the global base register value. Output instructions required to
222 /// initialize the register in the function entry block, if necessary.
224 unsigned getGlobalBaseReg(MachineFunction *MF) const;