1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "MipsRegisterInfo.h"
25 // Mips Condition Codes
36 // Turn condition code into conditional branch opcode.
37 unsigned GetCondBranchFromCond(CondCode CC);
39 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
40 /// e.g. turning COND_E to COND_NE.
41 CondCode GetOppositeBranchCondition(Mips::CondCode CC);
45 class MipsInstrInfo : public TargetInstrInfo
47 MipsTargetMachine &TM;
48 const MipsRegisterInfo RI;
50 MipsInstrInfo(MipsTargetMachine &TM);
52 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
53 /// such, whenever a client has an instance of instruction info, it should
54 /// always be able to get register info as well (through this method).
56 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
58 /// Return true if the instruction is a register to register move and
59 /// leave the source and dest operands in the passed parameters.
61 virtual bool isMoveInstr(const MachineInstr &MI,
62 unsigned &SrcReg, unsigned &DstReg) const;
64 /// isLoadFromStackSlot - If the specified machine instruction is a direct
65 /// load from a stack slot, return the virtual or physical register number of
66 /// the destination along with the FrameIndex of the loaded stack slot. If
67 /// not, return 0. This predicate must return 0 if the instruction has
68 /// any side effects other than loading from the stack slot.
69 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
71 /// isStoreToStackSlot - If the specified machine instruction is a direct
72 /// store to a stack slot, return the virtual or physical register number of
73 /// the source reg along with the FrameIndex of the loaded stack slot. If
74 /// not, return 0. This predicate must return 0 if the instruction has
75 /// any side effects other than storing to the stack slot.
76 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
79 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
80 MachineBasicBlock *&FBB,
81 std::vector<MachineOperand> &Cond) const;
82 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
83 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
84 MachineBasicBlock *FBB,
85 const std::vector<MachineOperand> &Cond) const;
86 virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
87 unsigned DestReg, unsigned SrcReg,
88 const TargetRegisterClass *DestRC,
89 const TargetRegisterClass *SrcRC) const;
90 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
91 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
93 /// Insert nop instruction when hazard condition is found
94 virtual void insertNoop(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MI) const;