1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
172 AssemblerPredicate<"FeatureMips16">;
173 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
174 AssemblerPredicate<"FeatureCnMips">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
190 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
252 def simm10 : Operand<i32>;
254 def simm16 : Operand<i32> {
255 let DecoderMethod= "DecodeSimm16";
258 def simm20 : Operand<i32> {
261 def uimm20 : Operand<i32> {
264 def uimm10 : Operand<i32> {
267 def simm16_64 : Operand<i64> {
268 let DecoderMethod = "DecodeSimm16";
272 def uimm5 : Operand<i32> {
273 let PrintMethod = "printUnsignedImm";
276 def uimm6 : Operand<i32> {
277 let PrintMethod = "printUnsignedImm";
280 def uimm16 : Operand<i32> {
281 let PrintMethod = "printUnsignedImm";
284 def pcrel16 : Operand<i32> {
287 def MipsMemAsmOperand : AsmOperandClass {
289 let ParserMethod = "parseMemOperand";
292 def MipsInvertedImmoperand : AsmOperandClass {
294 let RenderMethod = "addImmOperands";
295 let ParserMethod = "parseInvNum";
298 def PtrRegAsmOperand : AsmOperandClass {
300 let ParserMethod = "parsePtrReg";
304 def InvertedImOperand : Operand<i32> {
305 let ParserMatchClass = MipsInvertedImmoperand;
308 class mem_generic : Operand<iPTR> {
309 let PrintMethod = "printMemOperand";
310 let MIOperandInfo = (ops ptr_rc, simm16);
311 let EncoderMethod = "getMemEncoding";
312 let ParserMatchClass = MipsMemAsmOperand;
313 let OperandType = "OPERAND_MEMORY";
317 def mem : mem_generic;
319 // MSA specific address operand
320 def mem_msa : mem_generic {
321 let MIOperandInfo = (ops ptr_rc, simm10);
322 let EncoderMethod = "getMSAMemEncoding";
325 def mem_ea : Operand<iPTR> {
326 let PrintMethod = "printMemOperandEA";
327 let MIOperandInfo = (ops ptr_rc, simm16);
328 let EncoderMethod = "getMemEncoding";
329 let OperandType = "OPERAND_MEMORY";
332 def PtrRC : Operand<iPTR> {
333 let MIOperandInfo = (ops ptr_rc);
334 let DecoderMethod = "DecodePtrRegisterClass";
335 let ParserMatchClass = PtrRegAsmOperand;
338 // size operand of ext instruction
339 def size_ext : Operand<i32> {
340 let EncoderMethod = "getSizeExtEncoding";
341 let DecoderMethod = "DecodeExtSize";
344 // size operand of ins instruction
345 def size_ins : Operand<i32> {
346 let EncoderMethod = "getSizeInsEncoding";
347 let DecoderMethod = "DecodeInsSize";
350 // Transformation Function - get the lower 16 bits.
351 def LO16 : SDNodeXForm<imm, [{
352 return getImm(N, N->getZExtValue() & 0xFFFF);
355 // Transformation Function - get the higher 16 bits.
356 def HI16 : SDNodeXForm<imm, [{
357 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
361 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
363 // Node immediate fits as 16-bit sign extended on target immediate.
365 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
367 // Node immediate fits as 16-bit sign extended on target immediate.
369 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
371 // Node immediate fits as 15-bit sign extended on target immediate.
373 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
375 // Node immediate fits as 16-bit zero extended on target immediate.
376 // The LO16 param means that only the lower 16 bits of the node
377 // immediate are caught.
379 def immZExt16 : PatLeaf<(imm), [{
380 if (N->getValueType(0) == MVT::i32)
381 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
383 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
386 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
387 def immLow16Zero : PatLeaf<(imm), [{
388 int64_t Val = N->getSExtValue();
389 return isInt<32>(Val) && !(Val & 0xffff);
392 // shamt field must fit in 5 bits.
393 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
395 // True if (N + 1) fits in 16-bit field.
396 def immSExt16Plus1 : PatLeaf<(imm), [{
397 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
400 // Mips Address Mode! SDNode frameindex could possibily be a match
401 // since load and store instructions from stack used it.
403 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
406 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
409 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
412 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
414 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
416 //===----------------------------------------------------------------------===//
417 // Instructions specific format
418 //===----------------------------------------------------------------------===//
420 // Arithmetic and logical instructions with 3 register operands.
421 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
422 InstrItinClass Itin = NoItinerary,
423 SDPatternOperator OpNode = null_frag>:
424 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
425 !strconcat(opstr, "\t$rd, $rs, $rt"),
426 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
427 let isCommutable = isComm;
428 let isReMaterializable = 1;
429 let TwoOperandAliasConstraint = "$rd = $rs";
432 // Arithmetic and logical instructions with 2 register operands.
433 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
434 InstrItinClass Itin = NoItinerary,
435 SDPatternOperator imm_type = null_frag,
436 SDPatternOperator OpNode = null_frag> :
437 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
438 !strconcat(opstr, "\t$rt, $rs, $imm16"),
439 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
441 let isReMaterializable = 1;
442 let TwoOperandAliasConstraint = "$rs = $rt";
445 // Arithmetic Multiply ADD/SUB
446 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
447 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
448 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
449 let Defs = [HI0, LO0];
450 let Uses = [HI0, LO0];
451 let isCommutable = isComm;
455 class LogicNOR<string opstr, RegisterOperand RO>:
456 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
457 !strconcat(opstr, "\t$rd, $rs, $rt"),
458 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
459 let isCommutable = 1;
463 class shift_rotate_imm<string opstr, Operand ImmOpnd,
464 RegisterOperand RO, InstrItinClass itin,
465 SDPatternOperator OpNode = null_frag,
466 SDPatternOperator PF = null_frag> :
467 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
468 !strconcat(opstr, "\t$rd, $rt, $shamt"),
469 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
471 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
472 SDPatternOperator OpNode = null_frag>:
473 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
474 !strconcat(opstr, "\t$rd, $rt, $rs"),
475 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
478 // Load Upper Imediate
479 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
480 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
481 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
482 let neverHasSideEffects = 1;
483 let isReMaterializable = 1;
487 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
488 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
489 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
490 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
491 let DecoderMethod = "DecodeMem";
492 let canFoldAsLoad = 1;
496 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
497 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
498 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
499 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
500 let DecoderMethod = "DecodeMem";
504 // Load/Store Left/Right
505 let canFoldAsLoad = 1 in
506 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
507 InstrItinClass Itin> :
508 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
509 !strconcat(opstr, "\t$rt, $addr"),
510 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
511 let DecoderMethod = "DecodeMem";
512 string Constraints = "$src = $rt";
515 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
516 InstrItinClass Itin> :
517 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
518 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
519 let DecoderMethod = "DecodeMem";
522 // Conditional Branch
523 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
524 RegisterOperand RO> :
525 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
526 !strconcat(opstr, "\t$rs, $rt, $offset"),
527 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
530 let isTerminator = 1;
531 let hasDelaySlot = 1;
535 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
536 RegisterOperand RO> :
537 InstSE<(outs), (ins RO:$rs, opnd:$offset),
538 !strconcat(opstr, "\t$rs, $offset"),
539 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
542 let isTerminator = 1;
543 let hasDelaySlot = 1;
548 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
549 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
550 !strconcat(opstr, "\t$rd, $rs, $rt"),
551 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
552 II_SLT_SLTU, FrmR, opstr>;
554 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
556 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
557 !strconcat(opstr, "\t$rt, $rs, $imm16"),
558 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
559 II_SLTI_SLTIU, FrmI, opstr>;
562 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
563 SDPatternOperator targetoperator, string bopstr> :
564 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
565 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
568 let hasDelaySlot = 1;
569 let DecoderMethod = "DecodeJumpTarget";
573 // Unconditional branch
574 class UncondBranch<Instruction BEQInst> :
575 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
576 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
578 let isTerminator = 1;
580 let hasDelaySlot = 1;
581 let Predicates = [RelocPIC, HasStdEnc];
585 // Base class for indirect branch and return instruction classes.
586 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
587 class JumpFR<string opstr, RegisterOperand RO,
588 SDPatternOperator operator = null_frag>:
589 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
593 class IndirectBranch<string opstr, RegisterOperand RO> :
594 JumpFR<opstr, RO, brind> {
596 let isIndirectBranch = 1;
599 // Return instruction
600 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
602 let isCodeGenOnly = 1;
604 let hasExtraSrcRegAllocReq = 1;
607 // Jump and Link (Call)
608 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
609 class JumpLink<string opstr, DAGOperand opnd> :
610 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
611 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
612 let DecoderMethod = "DecodeJumpTarget";
615 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
616 Register RetReg, RegisterOperand ResRO = RO>:
617 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
618 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
620 class JumpLinkReg<string opstr, RegisterOperand RO>:
621 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
624 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
625 InstSE<(outs), (ins RO:$rs, opnd:$offset),
626 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
630 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
631 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
632 class TailCall<Instruction JumpInst> :
633 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
634 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
636 class TailCallReg<RegisterOperand RO, Instruction JRInst,
637 RegisterOperand ResRO = RO> :
638 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
639 PseudoInstExpansion<(JRInst ResRO:$rs)>;
642 class BAL_BR_Pseudo<Instruction RealInst> :
643 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
644 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
646 let isTerminator = 1;
648 let hasDelaySlot = 1;
653 class SYS_FT<string opstr> :
654 InstSE<(outs), (ins uimm20:$code_),
655 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
657 class BRK_FT<string opstr> :
658 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
659 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
663 class ER_FT<string opstr> :
664 InstSE<(outs), (ins),
665 opstr, [], NoItinerary, FrmOther, opstr>;
668 class DEI_FT<string opstr, RegisterOperand RO> :
669 InstSE<(outs RO:$rt), (ins),
670 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
673 class WAIT_FT<string opstr> :
674 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
677 let hasSideEffects = 1 in
678 class SYNC_FT<string opstr> :
679 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
680 NoItinerary, FrmOther, opstr>;
682 let hasSideEffects = 1 in
683 class TEQ_FT<string opstr, RegisterOperand RO> :
684 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
685 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
688 class TEQI_FT<string opstr, RegisterOperand RO> :
689 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
690 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
692 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
693 list<Register> DefRegs> :
694 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
696 let isCommutable = 1;
698 let neverHasSideEffects = 1;
701 // Pseudo multiply/divide instruction with explicit accumulator register
703 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
704 SDPatternOperator OpNode, InstrItinClass Itin,
705 bit IsComm = 1, bit HasSideEffects = 0,
706 bit UsesCustomInserter = 0> :
707 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
708 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
709 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
710 let isCommutable = IsComm;
711 let hasSideEffects = HasSideEffects;
712 let usesCustomInserter = UsesCustomInserter;
715 // Pseudo multiply add/sub instruction with explicit accumulator register
717 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
719 : PseudoSE<(outs ACC64:$ac),
720 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
722 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
724 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
725 string Constraints = "$acin = $ac";
728 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
729 list<Register> DefRegs> :
730 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
731 [], itin, FrmR, opstr> {
736 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
737 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
738 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
740 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
741 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
744 let neverHasSideEffects = 1;
747 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
748 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
749 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
752 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
753 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
756 let neverHasSideEffects = 1;
759 class EffectiveAddress<string opstr, RegisterOperand RO> :
760 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
761 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
762 !strconcat(opstr, "_lea")> {
763 let isCodeGenOnly = 1;
764 let DecoderMethod = "DecodeMem";
767 // Count Leading Ones/Zeros in Word
768 class CountLeading0<string opstr, RegisterOperand RO>:
769 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
770 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
771 Requires<[HasBitCount, HasStdEnc]>;
773 class CountLeading1<string opstr, RegisterOperand RO>:
774 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
775 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
776 Requires<[HasBitCount, HasStdEnc]>;
778 // Sign Extend in Register.
779 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
780 InstrItinClass itin> :
781 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
782 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
783 let Predicates = [HasSEInReg, HasStdEnc];
787 class SubwordSwap<string opstr, RegisterOperand RO>:
788 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
789 NoItinerary, FrmR, opstr> {
790 let Predicates = [HasSwap, HasStdEnc];
791 let neverHasSideEffects = 1;
795 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
796 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
800 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
801 SDPatternOperator Op = null_frag>:
802 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
803 !strconcat(opstr, " $rt, $rs, $pos, $size"),
804 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
806 let Predicates = [HasMips32r2, HasStdEnc];
809 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
810 SDPatternOperator Op = null_frag>:
811 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
812 !strconcat(opstr, " $rt, $rs, $pos, $size"),
813 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
814 NoItinerary, FrmR, opstr> {
815 let Predicates = [HasMips32r2, HasStdEnc];
816 let Constraints = "$src = $rt";
819 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
820 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
821 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
822 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
824 // Atomic Compare & Swap.
825 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
826 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
827 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
829 class LLBase<string opstr, RegisterOperand RO> :
830 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
831 [], NoItinerary, FrmI> {
832 let DecoderMethod = "DecodeMem";
836 class SCBase<string opstr, RegisterOperand RO> :
837 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
838 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
839 let DecoderMethod = "DecodeMem";
841 let Constraints = "$rt = $dst";
844 class MFC3OP<string asmstr, RegisterOperand RO> :
845 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
846 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
848 class TrapBase<Instruction RealInst>
849 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
850 PseudoInstExpansion<(RealInst 0, 0)> {
852 let isTerminator = 1;
853 let isCodeGenOnly = 1;
856 //===----------------------------------------------------------------------===//
857 // Pseudo instructions
858 //===----------------------------------------------------------------------===//
861 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
862 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
864 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
865 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
866 [(callseq_start timm:$amt)]>;
867 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
868 [(callseq_end timm:$amt1, timm:$amt2)]>;
871 let usesCustomInserter = 1 in {
872 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
873 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
874 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
875 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
876 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
877 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
878 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
879 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
880 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
881 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
882 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
883 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
884 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
885 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
886 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
887 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
888 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
889 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
891 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
892 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
893 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
895 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
896 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
897 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
900 /// Pseudo instructions for loading and storing accumulator registers.
901 let isPseudo = 1, isCodeGenOnly = 1 in {
902 def LOAD_ACC64 : Load<"", ACC64>;
903 def STORE_ACC64 : Store<"", ACC64>;
906 //===----------------------------------------------------------------------===//
907 // Instruction definition
908 //===----------------------------------------------------------------------===//
909 //===----------------------------------------------------------------------===//
910 // MipsI Instructions
911 //===----------------------------------------------------------------------===//
913 /// Arithmetic Instructions (ALU Immediate)
914 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
916 ADDI_FM<0x9>, IsAsCheapAsAMove;
917 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
918 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
920 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
922 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
925 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
928 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
931 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
933 /// Arithmetic Instructions (3-Operand, R-Type)
934 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
936 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
938 let Defs = [HI0, LO0] in
939 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
941 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
942 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
943 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
944 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
945 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
947 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
949 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
951 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
953 /// Shift Instructions
954 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
955 immZExt5>, SRA_FM<0, 0>;
956 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
957 immZExt5>, SRA_FM<2, 0>;
958 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
959 immZExt5>, SRA_FM<3, 0>;
960 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
962 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
964 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
967 // Rotate Instructions
968 let Predicates = [HasMips32r2, HasStdEnc] in {
969 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
970 immZExt5>, SRA_FM<2, 1>;
971 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
975 /// Load and Store Instructions
977 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
978 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
980 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
982 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
983 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
985 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
986 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
987 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
989 /// load/store left/right
990 let Predicates = [NotInMicroMips] in {
991 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
992 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
993 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
994 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
997 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
998 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
999 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1000 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1001 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1002 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1003 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1005 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1006 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1007 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1008 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1009 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1010 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1012 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1013 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1014 def TRAP : TrapBase<BREAK>;
1016 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1017 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1019 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1020 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1022 let Predicates = [NotInMicroMips] in {
1023 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1025 /// Load-linked, Store-conditional
1026 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1027 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1030 /// Jump and Branch Instructions
1031 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1032 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1033 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1034 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1035 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1036 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1038 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1040 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1042 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1044 def B : UncondBranch<BEQ>;
1046 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1047 let Predicates = [NotInMicroMips] in {
1048 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1050 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1051 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1052 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1053 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1054 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1055 def TAILCALL : TailCall<J>;
1056 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1058 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1060 // Exception handling related node and instructions.
1061 // The conversion sequence is:
1062 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1063 // MIPSeh_return -> (stack change + indirect branch)
1065 // MIPSeh_return takes the place of regular return instruction
1066 // but takes two arguments (V1, V0) which are used for storing
1067 // the offset and return address respectively.
1068 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1070 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1071 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1073 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1074 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1075 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1076 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1078 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1081 /// Multiply and Divide Instructions.
1082 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1084 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1086 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1088 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1091 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1092 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1093 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1094 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1096 /// Sign Ext In Register Instructions.
1097 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1098 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1101 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1102 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1104 /// Word Swap Bytes Within Halfwords
1105 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1108 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1110 // FrameIndexes are legalized when they are operands from load/store
1111 // instructions. The same not happens for stack address copies, so an
1112 // add op with mem ComplexPattern is used and the stack address copy
1113 // can be matched. It's similar to Sparc LEA_ADDRi
1114 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1117 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1118 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1119 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1120 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1122 let Predicates = [HasStdEnc, NotDSP] in {
1123 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1124 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1125 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1126 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1127 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1128 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1129 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1130 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1131 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1134 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1136 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1139 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1141 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1142 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1144 /// Move Control Registers From/To CPU Registers
1145 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1146 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1147 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1148 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1150 //===----------------------------------------------------------------------===//
1151 // Instruction aliases
1152 //===----------------------------------------------------------------------===//
1153 def : InstAlias<"move $dst, $src",
1154 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1155 Requires<[NotMips64, NotInMicroMips]>;
1156 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1157 def : InstAlias<"addu $rs, $rt, $imm",
1158 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1159 def : InstAlias<"add $rs, $rt, $imm",
1160 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1161 def : InstAlias<"and $rs, $rt, $imm",
1162 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1163 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1164 let Predicates = [NotInMicroMips] in {
1165 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1167 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1168 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1169 def : InstAlias<"not $rt, $rs",
1170 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1171 def : InstAlias<"neg $rt, $rs",
1172 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1173 def : InstAlias<"negu $rt, $rs",
1174 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1175 def : InstAlias<"slt $rs, $rt, $imm",
1176 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1177 def : InstAlias<"xor $rs, $rt, $imm",
1178 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1179 def : InstAlias<"or $rs, $rt, $imm",
1180 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1181 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1182 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1183 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1184 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1185 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1186 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1187 def : InstAlias<"bnez $rs,$offset",
1188 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1189 def : InstAlias<"beqz $rs,$offset",
1190 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1191 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1193 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1194 def : InstAlias<"break", (BREAK 0, 0), 1>;
1195 def : InstAlias<"ei", (EI ZERO), 1>;
1196 def : InstAlias<"di", (DI ZERO), 1>;
1198 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1199 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1200 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1201 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1202 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1203 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1204 def : InstAlias<"sub, $rd, $rs, $imm",
1205 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1206 def : InstAlias<"subu, $rd, $rs, $imm",
1207 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1209 //===----------------------------------------------------------------------===//
1210 // Assembler Pseudo Instructions
1211 //===----------------------------------------------------------------------===//
1213 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1214 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1215 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1216 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1218 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1219 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1220 !strconcat(instr_asm, "\t$rt, $addr")> ;
1221 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1223 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1224 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1225 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1226 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1228 //===----------------------------------------------------------------------===//
1229 // Arbitrary patterns that map to one or more instructions
1230 //===----------------------------------------------------------------------===//
1232 // Load/store pattern templates.
1233 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1234 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1236 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1237 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1240 def : MipsPat<(i32 immSExt16:$in),
1241 (ADDiu ZERO, imm:$in)>;
1242 def : MipsPat<(i32 immZExt16:$in),
1243 (ORi ZERO, imm:$in)>;
1244 def : MipsPat<(i32 immLow16Zero:$in),
1245 (LUi (HI16 imm:$in))>;
1247 // Arbitrary immediates
1248 def : MipsPat<(i32 imm:$imm),
1249 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1251 // Carry MipsPatterns
1252 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1253 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1254 let Predicates = [HasStdEnc, NotDSP] in {
1255 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1256 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1257 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1258 (ADDiu GPR32:$src, imm:$imm)>;
1262 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1263 (JAL tglobaladdr:$dst)>;
1264 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1265 (JAL texternalsym:$dst)>;
1266 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1267 // (JALR GPR32:$dst)>;
1270 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1271 (TAILCALL tglobaladdr:$dst)>;
1272 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1273 (TAILCALL texternalsym:$dst)>;
1275 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1276 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1277 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1278 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1279 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1280 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1282 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1283 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1284 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1285 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1286 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1287 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1289 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1290 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1291 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1292 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1293 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1294 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1295 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1296 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1297 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1298 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1301 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1302 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1303 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1304 (ADDiu GPR32:$gp, tconstpool:$in)>;
1307 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1308 MipsPat<(MipsWrapper RC:$gp, node:$in),
1309 (ADDiuOp RC:$gp, node:$in)>;
1311 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1312 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1313 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1314 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1315 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1316 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1318 // Mips does not have "not", so we expand our way
1319 def : MipsPat<(not GPR32:$in),
1320 (NOR GPR32Opnd:$in, ZERO)>;
1323 let Predicates = [HasStdEnc] in {
1324 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1325 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1326 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1330 let Predicates = [HasStdEnc] in
1331 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1334 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1335 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1336 Instruction SLTiuOp, Register ZEROReg> {
1337 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1338 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1339 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1340 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1342 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1343 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1344 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1345 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1346 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1347 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1348 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1349 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1350 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1351 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1352 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1353 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1355 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1356 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1357 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1358 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1360 def : MipsPat<(brcond RC:$cond, bb:$dst),
1361 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1364 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1366 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1367 (BLEZ i32:$lhs, bb:$dst)>;
1368 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1369 (BGEZ i32:$lhs, bb:$dst)>;
1372 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1373 Instruction SLTuOp, Register ZEROReg> {
1374 def : MipsPat<(seteq RC:$lhs, 0),
1375 (SLTiuOp RC:$lhs, 1)>;
1376 def : MipsPat<(setne RC:$lhs, 0),
1377 (SLTuOp ZEROReg, RC:$lhs)>;
1378 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1379 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1380 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1381 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1384 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1385 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1386 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1387 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1388 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1391 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1392 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1393 (SLTOp RC:$rhs, RC:$lhs)>;
1394 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1395 (SLTuOp RC:$rhs, RC:$lhs)>;
1398 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1399 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1400 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1401 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1402 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1405 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1406 Instruction SLTiuOp> {
1407 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1408 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1409 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1410 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1413 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1414 defm : SetlePats<GPR32, SLT, SLTu>;
1415 defm : SetgtPats<GPR32, SLT, SLTu>;
1416 defm : SetgePats<GPR32, SLT, SLTu>;
1417 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1420 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1422 // Load halfword/word patterns.
1423 let AddedComplexity = 40 in {
1424 let Predicates = [HasStdEnc] in {
1425 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1426 def : LoadRegImmPat<LH, i32, sextloadi16>;
1427 def : LoadRegImmPat<LW, i32, load>;
1431 //===----------------------------------------------------------------------===//
1432 // Floating Point Support
1433 //===----------------------------------------------------------------------===//
1435 include "MipsInstrFPU.td"
1436 include "Mips64InstrInfo.td"
1437 include "MipsCondMov.td"
1442 include "Mips16InstrFormats.td"
1443 include "Mips16InstrInfo.td"
1446 include "MipsDSPInstrFormats.td"
1447 include "MipsDSPInstrInfo.td"
1450 include "MipsMSAInstrFormats.td"
1451 include "MipsMSAInstrInfo.td"
1454 include "MicroMipsInstrFormats.td"
1455 include "MicroMipsInstrInfo.td"
1456 include "MicroMipsInstrFPU.td"