1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"FeatureMips32r6">;
171 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"!FeatureMips32r6">;
173 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
174 AssemblerPredicate<"FeatureGP64Bit">;
175 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
176 AssemblerPredicate<"!FeatureGP64Bit">;
177 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
178 AssemblerPredicate<"FeatureMips64">;
179 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
180 AssemblerPredicate<"FeatureMips64r2">;
181 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"FeatureMips64r6">;
183 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"!FeatureMips64r6">;
185 def IsN64 : Predicate<"Subtarget->isABI_N64()">,
186 AssemblerPredicate<"FeatureN64">;
187 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
188 AssemblerPredicate<"FeatureMips16">;
189 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
190 AssemblerPredicate<"FeatureCnMips">;
191 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
192 AssemblerPredicate<"FeatureMips32">;
193 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
194 AssemblerPredicate<"FeatureMips32">;
195 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
196 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
197 AssemblerPredicate<"!FeatureMips16">;
198 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
199 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"FeatureMicroMips">;
201 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
202 AssemblerPredicate<"!FeatureMicroMips">;
203 def IsLE : Predicate<"Subtarget->isLittle()">;
204 def IsBE : Predicate<"!Subtarget->isLittle()">;
205 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
207 //===----------------------------------------------------------------------===//
208 // Mips GPR size adjectives.
209 // They are mutually exclusive.
210 //===----------------------------------------------------------------------===//
212 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
213 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
215 //===----------------------------------------------------------------------===//
216 // Mips ISA/ASE membership and instruction group membership adjectives.
217 // They are mutually exclusive.
218 //===----------------------------------------------------------------------===//
220 // FIXME: I'd prefer to use additive predicates to build the instruction sets
221 // but we are short on assembler feature bits at the moment. Using a
222 // subtractive predicate will hopefully keep us under the 32 predicate
223 // limit long enough to develop an alternative way to handle P1||P2
225 class ISA_MIPS1_NOT_4_32 {
226 list<Predicate> InsnPredicates = [NotMips4_32];
228 class ISA_MIPS1_NOT_32R6_64R6 {
229 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
231 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
232 class ISA_MIPS2_NOT_32R6_64R6 {
233 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
235 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
236 class ISA_MIPS3_NOT_32R6_64R6 {
237 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
239 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
240 class ISA_MIPS32_NOT_32R6_64R6 {
241 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
243 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
244 class ISA_MIPS32R2_NOT_32R6_64R6 {
245 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
247 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
248 class ISA_MIPS64_NOT_64R6 {
249 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
251 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
252 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
253 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
255 // The portions of MIPS-III that were also added to MIPS32
256 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
258 // The portions of MIPS-III that were also added to MIPS32 but were removed in
259 // MIPS32r6 and MIPS64r6.
260 class INSN_MIPS3_32_NOT_32R6_64R6 {
261 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
264 // The portions of MIPS-III that were also added to MIPS32
265 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
267 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
268 // MIPS32r6 and MIPS64r6.
269 class INSN_MIPS4_32_NOT_32R6_64R6 {
270 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
273 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
274 // MIPS32r6 and MIPS64r6.
275 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
276 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
279 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
280 // MIPS32r6 and MIPS64r6.
281 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
282 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
285 //===----------------------------------------------------------------------===//
287 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
288 let EncodingPredicates = [HasStdEnc];
291 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
292 InstAlias<Asm, Result, Emit>, PredicateControl;
295 bit isCommutable = 1;
312 bit isTerminator = 1;
315 bit hasExtraSrcRegAllocReq = 1;
316 bit isCodeGenOnly = 1;
319 class IsAsCheapAsAMove {
320 bit isAsCheapAsAMove = 1;
323 class NeverHasSideEffects {
324 bit hasSideEffects = 0;
327 //===----------------------------------------------------------------------===//
328 // Instruction format superclass
329 //===----------------------------------------------------------------------===//
331 include "MipsInstrFormats.td"
333 //===----------------------------------------------------------------------===//
334 // Mips Operand, Complex Patterns and Transformations Definitions.
335 //===----------------------------------------------------------------------===//
337 def MipsJumpTargetAsmOperand : AsmOperandClass {
338 let Name = "JumpTarget";
339 let ParserMethod = "parseJumpTarget";
340 let PredicateMethod = "isImm";
341 let RenderMethod = "addImmOperands";
344 // Instruction operand types
345 def jmptarget : Operand<OtherVT> {
346 let EncoderMethod = "getJumpTargetOpValue";
347 let ParserMatchClass = MipsJumpTargetAsmOperand;
349 def brtarget : Operand<OtherVT> {
350 let EncoderMethod = "getBranchTargetOpValue";
351 let OperandType = "OPERAND_PCREL";
352 let DecoderMethod = "DecodeBranchTarget";
353 let ParserMatchClass = MipsJumpTargetAsmOperand;
355 def calltarget : Operand<iPTR> {
356 let EncoderMethod = "getJumpTargetOpValue";
357 let ParserMatchClass = MipsJumpTargetAsmOperand;
360 def simm9 : Operand<i32>;
361 def simm10 : Operand<i32>;
362 def simm11 : Operand<i32>;
364 def simm16 : Operand<i32> {
365 let DecoderMethod= "DecodeSimm16";
368 def simm19_lsl2 : Operand<i32> {
369 let EncoderMethod = "getSimm19Lsl2Encoding";
370 let DecoderMethod = "DecodeSimm19Lsl2";
371 let ParserMatchClass = MipsJumpTargetAsmOperand;
374 def simm18_lsl3 : Operand<i32> {
375 let EncoderMethod = "getSimm18Lsl3Encoding";
376 let DecoderMethod = "DecodeSimm18Lsl3";
377 let ParserMatchClass = MipsJumpTargetAsmOperand;
380 def simm20 : Operand<i32> {
383 def uimm20 : Operand<i32> {
386 def uimm10 : Operand<i32> {
389 def simm16_64 : Operand<i64> {
390 let DecoderMethod = "DecodeSimm16";
394 def uimmz : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
399 def uimm2 : Operand<i32> {
400 let PrintMethod = "printUnsignedImm";
403 def uimm3 : Operand<i32> {
404 let PrintMethod = "printUnsignedImm";
407 def uimm5 : Operand<i32> {
408 let PrintMethod = "printUnsignedImm";
411 def uimm6 : Operand<i32> {
412 let PrintMethod = "printUnsignedImm";
415 def uimm16 : Operand<i32> {
416 let PrintMethod = "printUnsignedImm";
419 def pcrel16 : Operand<i32> {
422 def MipsMemAsmOperand : AsmOperandClass {
424 let ParserMethod = "parseMemOperand";
427 def MipsMemSimm11AsmOperand : AsmOperandClass {
428 let Name = "MemOffsetSimm11";
429 let SuperClasses = [MipsMemAsmOperand];
430 let RenderMethod = "addMemOperands";
431 let ParserMethod = "parseMemOperand";
432 let PredicateMethod = "isMemWithSimmOffset<11>";
435 def MipsMemSimm16AsmOperand : AsmOperandClass {
436 let Name = "MemOffsetSimm16";
437 let SuperClasses = [MipsMemAsmOperand];
438 let RenderMethod = "addMemOperands";
439 let ParserMethod = "parseMemOperand";
440 let PredicateMethod = "isMemWithSimmOffset<16>";
443 def MipsInvertedImmoperand : AsmOperandClass {
445 let RenderMethod = "addImmOperands";
446 let ParserMethod = "parseInvNum";
449 def InvertedImOperand : Operand<i32> {
450 let ParserMatchClass = MipsInvertedImmoperand;
453 def InvertedImOperand64 : Operand<i64> {
454 let ParserMatchClass = MipsInvertedImmoperand;
457 class mem_generic : Operand<iPTR> {
458 let PrintMethod = "printMemOperand";
459 let MIOperandInfo = (ops ptr_rc, simm16);
460 let EncoderMethod = "getMemEncoding";
461 let ParserMatchClass = MipsMemAsmOperand;
462 let OperandType = "OPERAND_MEMORY";
466 def mem : mem_generic;
468 // MSA specific address operand
469 def mem_msa : mem_generic {
470 let MIOperandInfo = (ops ptr_rc, simm10);
471 let EncoderMethod = "getMSAMemEncoding";
474 def mem_simm9 : mem_generic {
475 let MIOperandInfo = (ops ptr_rc, simm9);
476 let EncoderMethod = "getMemEncoding";
479 def mem_simm11 : mem_generic {
480 let MIOperandInfo = (ops ptr_rc, simm11);
481 let EncoderMethod = "getMemEncoding";
482 let ParserMatchClass = MipsMemSimm11AsmOperand;
485 def mem_simm16 : mem_generic {
486 let MIOperandInfo = (ops ptr_rc, simm16);
487 let EncoderMethod = "getMemEncoding";
488 let ParserMatchClass = MipsMemSimm16AsmOperand;
491 def mem_ea : Operand<iPTR> {
492 let PrintMethod = "printMemOperandEA";
493 let MIOperandInfo = (ops ptr_rc, simm16);
494 let EncoderMethod = "getMemEncoding";
495 let OperandType = "OPERAND_MEMORY";
498 def PtrRC : Operand<iPTR> {
499 let MIOperandInfo = (ops ptr_rc);
500 let DecoderMethod = "DecodePtrRegisterClass";
501 let ParserMatchClass = GPR32AsmOperand;
504 // size operand of ext instruction
505 def size_ext : Operand<i32> {
506 let EncoderMethod = "getSizeExtEncoding";
507 let DecoderMethod = "DecodeExtSize";
510 // size operand of ins instruction
511 def size_ins : Operand<i32> {
512 let EncoderMethod = "getSizeInsEncoding";
513 let DecoderMethod = "DecodeInsSize";
516 // Transformation Function - get the lower 16 bits.
517 def LO16 : SDNodeXForm<imm, [{
518 return getImm(N, N->getZExtValue() & 0xFFFF);
521 // Transformation Function - get the higher 16 bits.
522 def HI16 : SDNodeXForm<imm, [{
523 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
527 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
529 // Node immediate is zero (e.g. insve.d)
530 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
532 // Node immediate fits as 16-bit sign extended on target immediate.
534 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
536 // Node immediate fits as 16-bit sign extended on target immediate.
538 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
540 // Node immediate fits as 15-bit sign extended on target immediate.
542 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
544 // Node immediate fits as 16-bit zero extended on target immediate.
545 // The LO16 param means that only the lower 16 bits of the node
546 // immediate are caught.
548 def immZExt16 : PatLeaf<(imm), [{
549 if (N->getValueType(0) == MVT::i32)
550 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
552 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
555 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
556 def immLow16Zero : PatLeaf<(imm), [{
557 int64_t Val = N->getSExtValue();
558 return isInt<32>(Val) && !(Val & 0xffff);
561 // shamt field must fit in 5 bits.
562 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
564 // True if (N + 1) fits in 16-bit field.
565 def immSExt16Plus1 : PatLeaf<(imm), [{
566 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
569 // Mips Address Mode! SDNode frameindex could possibily be a match
570 // since load and store instructions from stack used it.
572 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
575 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
578 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
581 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
583 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
585 //===----------------------------------------------------------------------===//
586 // Instructions specific format
587 //===----------------------------------------------------------------------===//
589 // Arithmetic and logical instructions with 3 register operands.
590 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
591 InstrItinClass Itin = NoItinerary,
592 SDPatternOperator OpNode = null_frag>:
593 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
594 !strconcat(opstr, "\t$rd, $rs, $rt"),
595 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
596 let isCommutable = isComm;
597 let isReMaterializable = 1;
598 let TwoOperandAliasConstraint = "$rd = $rs";
601 // Arithmetic and logical instructions with 2 register operands.
602 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
603 InstrItinClass Itin = NoItinerary,
604 SDPatternOperator imm_type = null_frag,
605 SDPatternOperator OpNode = null_frag> :
606 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
607 !strconcat(opstr, "\t$rt, $rs, $imm16"),
608 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
610 let isReMaterializable = 1;
611 let TwoOperandAliasConstraint = "$rs = $rt";
614 // Arithmetic Multiply ADD/SUB
615 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
616 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
617 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
618 let Defs = [HI0, LO0];
619 let Uses = [HI0, LO0];
620 let isCommutable = isComm;
624 class LogicNOR<string opstr, RegisterOperand RO>:
625 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
626 !strconcat(opstr, "\t$rd, $rs, $rt"),
627 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
628 let isCommutable = 1;
632 class shift_rotate_imm<string opstr, Operand ImmOpnd,
633 RegisterOperand RO, InstrItinClass itin,
634 SDPatternOperator OpNode = null_frag,
635 SDPatternOperator PF = null_frag> :
636 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
637 !strconcat(opstr, "\t$rd, $rt, $shamt"),
638 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
639 let TwoOperandAliasConstraint = "$rt = $rd";
642 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
643 SDPatternOperator OpNode = null_frag>:
644 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
645 !strconcat(opstr, "\t$rd, $rt, $rs"),
646 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
649 // Load Upper Imediate
650 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
651 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
652 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
653 let hasSideEffects = 0;
654 let isReMaterializable = 1;
658 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
659 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
660 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
661 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
662 let DecoderMethod = "DecodeMem";
663 let canFoldAsLoad = 1;
667 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
668 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
669 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
670 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
671 let DecoderMethod = "DecodeMem";
675 // Load/Store Left/Right
676 let canFoldAsLoad = 1 in
677 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
678 InstrItinClass Itin> :
679 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
680 !strconcat(opstr, "\t$rt, $addr"),
681 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
682 let DecoderMethod = "DecodeMem";
683 string Constraints = "$src = $rt";
686 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
687 InstrItinClass Itin> :
688 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
689 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
690 let DecoderMethod = "DecodeMem";
694 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
695 SDPatternOperator OpNode= null_frag> :
696 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
697 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
698 let DecoderMethod = "DecodeFMem2";
702 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
703 SDPatternOperator OpNode= null_frag> :
704 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
705 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
706 let DecoderMethod = "DecodeFMem2";
711 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
712 SDPatternOperator OpNode= null_frag> :
713 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
714 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
715 let DecoderMethod = "DecodeFMem3";
719 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
720 SDPatternOperator OpNode= null_frag> :
721 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
722 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
723 let DecoderMethod = "DecodeFMem3";
727 // Conditional Branch
728 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
729 RegisterOperand RO, bit DelaySlot = 1> :
730 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
731 !strconcat(opstr, "\t$rs, $rt, $offset"),
732 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
735 let isTerminator = 1;
736 let hasDelaySlot = DelaySlot;
740 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
741 RegisterOperand RO, bit DelaySlot = 1> :
742 InstSE<(outs), (ins RO:$rs, opnd:$offset),
743 !strconcat(opstr, "\t$rs, $offset"),
744 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
747 let isTerminator = 1;
748 let hasDelaySlot = DelaySlot;
753 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
754 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
755 !strconcat(opstr, "\t$rd, $rs, $rt"),
756 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
757 II_SLT_SLTU, FrmR, opstr>;
759 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
761 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
762 !strconcat(opstr, "\t$rt, $rs, $imm16"),
763 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
764 II_SLTI_SLTIU, FrmI, opstr>;
767 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
768 SDPatternOperator targetoperator, string bopstr> :
769 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
770 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
773 let hasDelaySlot = 1;
774 let DecoderMethod = "DecodeJumpTarget";
778 // Unconditional branch
779 class UncondBranch<Instruction BEQInst> :
780 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
781 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
783 let isTerminator = 1;
785 let hasDelaySlot = 1;
786 let AdditionalPredicates = [RelocPIC];
790 // Base class for indirect branch and return instruction classes.
791 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
792 class JumpFR<string opstr, RegisterOperand RO,
793 SDPatternOperator operator = null_frag>:
794 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
798 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
800 let isIndirectBranch = 1;
803 // Jump and Link (Call)
804 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
805 class JumpLink<string opstr, DAGOperand opnd> :
806 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
807 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
808 let DecoderMethod = "DecodeJumpTarget";
811 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
812 Register RetReg, RegisterOperand ResRO = RO>:
813 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
814 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
816 class JumpLinkReg<string opstr, RegisterOperand RO>:
817 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
820 class BGEZAL_FT<string opstr, DAGOperand opnd,
821 RegisterOperand RO, bit DelaySlot = 1> :
822 InstSE<(outs), (ins RO:$rs, opnd:$offset),
823 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
824 let hasDelaySlot = DelaySlot;
829 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
830 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
831 class TailCall<Instruction JumpInst> :
832 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
833 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
835 class TailCallReg<RegisterOperand RO, Instruction JRInst,
836 RegisterOperand ResRO = RO> :
837 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
838 PseudoInstExpansion<(JRInst ResRO:$rs)>;
841 class BAL_BR_Pseudo<Instruction RealInst> :
842 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
843 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
845 let isTerminator = 1;
847 let hasDelaySlot = 1;
852 class SYS_FT<string opstr> :
853 InstSE<(outs), (ins uimm20:$code_),
854 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
856 class BRK_FT<string opstr> :
857 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
858 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
862 class ER_FT<string opstr> :
863 InstSE<(outs), (ins),
864 opstr, [], NoItinerary, FrmOther, opstr>;
867 class DEI_FT<string opstr, RegisterOperand RO> :
868 InstSE<(outs RO:$rt), (ins),
869 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
872 class WAIT_FT<string opstr> :
873 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
876 let hasSideEffects = 1 in
877 class SYNC_FT<string opstr> :
878 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
879 NoItinerary, FrmOther, opstr>;
881 class SYNCI_FT<string opstr> :
882 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
883 NoItinerary, FrmOther, opstr> {
884 let hasSideEffects = 1;
885 let DecoderMethod = "DecodeSyncI";
888 let hasSideEffects = 1 in
889 class TEQ_FT<string opstr, RegisterOperand RO> :
890 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
891 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
894 class TEQI_FT<string opstr, RegisterOperand RO> :
895 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
896 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
898 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
899 list<Register> DefRegs> :
900 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
902 let isCommutable = 1;
904 let hasSideEffects = 0;
907 // Pseudo multiply/divide instruction with explicit accumulator register
909 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
910 SDPatternOperator OpNode, InstrItinClass Itin,
911 bit IsComm = 1, bit HasSideEffects = 0,
912 bit UsesCustomInserter = 0> :
913 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
914 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
915 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
916 let isCommutable = IsComm;
917 let hasSideEffects = HasSideEffects;
918 let usesCustomInserter = UsesCustomInserter;
921 // Pseudo multiply add/sub instruction with explicit accumulator register
923 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
925 : PseudoSE<(outs ACC64:$ac),
926 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
928 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
930 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
931 string Constraints = "$acin = $ac";
934 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
935 list<Register> DefRegs> :
936 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
937 [], itin, FrmR, opstr> {
942 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
943 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
944 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
946 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
947 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
950 let hasSideEffects = 0;
953 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
954 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
955 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
958 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
959 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
962 let hasSideEffects = 0;
965 class EffectiveAddress<string opstr, RegisterOperand RO> :
966 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
967 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
968 !strconcat(opstr, "_lea")> {
969 let isCodeGenOnly = 1;
970 let DecoderMethod = "DecodeMem";
973 // Count Leading Ones/Zeros in Word
974 class CountLeading0<string opstr, RegisterOperand RO>:
975 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
976 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
978 class CountLeading1<string opstr, RegisterOperand RO>:
979 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
980 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
982 // Sign Extend in Register.
983 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
984 InstrItinClass itin> :
985 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
986 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
989 class SubwordSwap<string opstr, RegisterOperand RO>:
990 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
991 NoItinerary, FrmR, opstr> {
992 let hasSideEffects = 0;
996 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
997 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
998 II_RDHWR, FrmR, "rdhwr">;
1001 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1002 SDPatternOperator Op = null_frag>:
1003 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1004 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1005 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
1006 FrmR, opstr>, ISA_MIPS32R2;
1008 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1009 SDPatternOperator Op = null_frag>:
1010 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1011 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1012 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1013 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
1014 let Constraints = "$src = $rt";
1017 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1018 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1019 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1020 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1022 // Atomic Compare & Swap.
1023 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1024 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1025 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1027 class LLBase<string opstr, RegisterOperand RO> :
1028 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1029 [], NoItinerary, FrmI> {
1030 let DecoderMethod = "DecodeMem";
1034 class SCBase<string opstr, RegisterOperand RO> :
1035 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1036 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1037 let DecoderMethod = "DecodeMem";
1039 let Constraints = "$rt = $dst";
1042 class MFC3OP<string asmstr, RegisterOperand RO> :
1043 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
1044 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1046 class TrapBase<Instruction RealInst>
1047 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1048 PseudoInstExpansion<(RealInst 0, 0)> {
1050 let isTerminator = 1;
1051 let isCodeGenOnly = 1;
1054 //===----------------------------------------------------------------------===//
1055 // Pseudo instructions
1056 //===----------------------------------------------------------------------===//
1059 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1060 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1062 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1063 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1064 [(callseq_start timm:$amt)]>;
1065 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1066 [(callseq_end timm:$amt1, timm:$amt2)]>;
1069 let usesCustomInserter = 1 in {
1070 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1071 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1072 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1073 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1074 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1075 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1076 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1077 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1078 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1079 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1080 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1081 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1082 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1083 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1084 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1085 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1086 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1087 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1089 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1090 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1091 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1093 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1094 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1095 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1098 /// Pseudo instructions for loading and storing accumulator registers.
1099 let isPseudo = 1, isCodeGenOnly = 1 in {
1100 def LOAD_ACC64 : Load<"", ACC64>;
1101 def STORE_ACC64 : Store<"", ACC64>;
1104 // We need these two pseudo instructions to avoid offset calculation for long
1105 // branches. See the comment in file MipsLongBranch.cpp for detailed
1108 // Expands to: lui $dst, %hi($tgt - $baltgt)
1109 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1110 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1112 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1113 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1114 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1116 //===----------------------------------------------------------------------===//
1117 // Instruction definition
1118 //===----------------------------------------------------------------------===//
1119 //===----------------------------------------------------------------------===//
1120 // MipsI Instructions
1121 //===----------------------------------------------------------------------===//
1123 /// Arithmetic Instructions (ALU Immediate)
1124 let AdditionalPredicates = [NotInMicroMips] in {
1125 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1126 add>, ADDI_FM<0x9>, IsAsCheapAsAMove;
1128 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1129 ISA_MIPS1_NOT_32R6_64R6;
1130 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1132 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1134 let AdditionalPredicates = [NotInMicroMips] in {
1135 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1138 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1141 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1144 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1146 /// Arithmetic Instructions (3-Operand, R-Type)
1147 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1149 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1151 let Defs = [HI0, LO0] in
1152 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1153 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1154 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1155 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1156 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1157 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1158 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1160 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1162 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1164 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1166 /// Shift Instructions
1167 let AdditionalPredicates = [NotInMicroMips] in {
1168 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1169 immZExt5>, SRA_FM<0, 0>;
1170 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1171 immZExt5>, SRA_FM<2, 0>;
1173 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1174 immZExt5>, SRA_FM<3, 0>;
1175 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1177 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1179 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1182 // Rotate Instructions
1183 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1185 SRA_FM<2, 1>, ISA_MIPS32R2;
1186 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1187 SRLV_FM<6, 1>, ISA_MIPS32R2;
1189 /// Load and Store Instructions
1191 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1192 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1194 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1196 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1197 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1199 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1200 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1201 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1203 /// load/store left/right
1204 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1205 AdditionalPredicates = [NotInMicroMips] in {
1206 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1207 ISA_MIPS1_NOT_32R6_64R6;
1208 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1209 ISA_MIPS1_NOT_32R6_64R6;
1210 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1211 ISA_MIPS1_NOT_32R6_64R6;
1212 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1213 ISA_MIPS1_NOT_32R6_64R6;
1216 // COP2 Memory Instructions
1217 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1218 ISA_MIPS1_NOT_32R6_64R6;
1219 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1220 ISA_MIPS1_NOT_32R6_64R6;
1221 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1222 ISA_MIPS2_NOT_32R6_64R6;
1223 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1224 ISA_MIPS2_NOT_32R6_64R6;
1226 // COP3 Memory Instructions
1227 let DecoderNamespace = "COP3_" in {
1228 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1229 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1230 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1232 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1236 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1237 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1239 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1240 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1241 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1242 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1243 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1244 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1246 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1247 ISA_MIPS2_NOT_32R6_64R6;
1248 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1249 ISA_MIPS2_NOT_32R6_64R6;
1250 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1251 ISA_MIPS2_NOT_32R6_64R6;
1252 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1253 ISA_MIPS2_NOT_32R6_64R6;
1254 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1255 ISA_MIPS2_NOT_32R6_64R6;
1256 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1257 ISA_MIPS2_NOT_32R6_64R6;
1259 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1260 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1261 def TRAP : TrapBase<BREAK>;
1262 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1264 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1265 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1267 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1268 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1270 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1271 AdditionalPredicates = [NotInMicroMips] in {
1272 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1274 /// Load-linked, Store-conditional
1275 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1276 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1279 /// Jump and Branch Instructions
1280 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1281 AdditionalRequires<[RelocStatic]>, IsBranch;
1282 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1283 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1284 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1285 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1286 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1287 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1288 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1289 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1291 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1292 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1293 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1295 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1296 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1297 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1299 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1300 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1301 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1303 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1304 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1305 def B : UncondBranch<BEQ>;
1307 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1308 let AdditionalPredicates = [NotInMicroMips] in {
1309 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1310 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1313 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1314 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1315 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1316 ISA_MIPS1_NOT_32R6_64R6;
1317 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1318 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1319 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1320 ISA_MIPS1_NOT_32R6_64R6;
1321 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1322 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1323 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1324 def TAILCALL : TailCall<J>;
1325 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1327 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1328 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1329 class PseudoIndirectBranchBase<RegisterOperand RO> :
1330 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1333 let hasDelaySlot = 1;
1335 let isIndirectBranch = 1;
1338 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1340 // Return instructions are matched as a RetRA instruction, then ar expanded
1341 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1342 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1344 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1346 let isTerminator = 1;
1348 let hasDelaySlot = 1;
1350 let isCodeGenOnly = 1;
1352 let hasExtraSrcRegAllocReq = 1;
1355 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1357 // Exception handling related node and instructions.
1358 // The conversion sequence is:
1359 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1360 // MIPSeh_return -> (stack change + indirect branch)
1362 // MIPSeh_return takes the place of regular return instruction
1363 // but takes two arguments (V1, V0) which are used for storing
1364 // the offset and return address respectively.
1365 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1367 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1368 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1370 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1371 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1372 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1373 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1375 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1378 /// Multiply and Divide Instructions.
1379 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1380 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1381 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1382 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1383 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1384 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1385 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1386 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1388 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1389 ISA_MIPS1_NOT_32R6_64R6;
1390 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1391 ISA_MIPS1_NOT_32R6_64R6;
1392 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1393 AdditionalPredicates = [NotInMicroMips] in {
1394 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1395 ISA_MIPS1_NOT_32R6_64R6;
1396 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1397 ISA_MIPS1_NOT_32R6_64R6;
1400 /// Sign Ext In Register Instructions.
1401 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1402 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1403 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1404 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1407 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1408 ISA_MIPS32_NOT_32R6_64R6;
1409 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1410 ISA_MIPS32_NOT_32R6_64R6;
1412 /// Word Swap Bytes Within Halfwords
1413 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1416 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1418 // FrameIndexes are legalized when they are operands from load/store
1419 // instructions. The same not happens for stack address copies, so an
1420 // add op with mem ComplexPattern is used and the stack address copy
1421 // can be matched. It's similar to Sparc LEA_ADDRi
1422 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1425 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1426 ISA_MIPS32_NOT_32R6_64R6;
1427 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1428 ISA_MIPS32_NOT_32R6_64R6;
1429 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1430 ISA_MIPS32_NOT_32R6_64R6;
1431 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1432 ISA_MIPS32_NOT_32R6_64R6;
1434 let AdditionalPredicates = [NotDSP] in {
1435 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1436 ISA_MIPS1_NOT_32R6_64R6;
1437 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1438 ISA_MIPS1_NOT_32R6_64R6;
1439 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1440 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1441 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1442 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1443 ISA_MIPS32_NOT_32R6_64R6;
1444 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1445 ISA_MIPS32_NOT_32R6_64R6;
1446 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1447 ISA_MIPS32_NOT_32R6_64R6;
1448 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1449 ISA_MIPS32_NOT_32R6_64R6;
1452 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1453 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1454 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1455 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1457 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1459 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1460 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1462 /// Move Control Registers From/To CPU Registers
1463 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1464 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1465 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1466 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1468 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1470 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1471 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1472 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1474 // JR_HB and JALR_HB are defined here using the new style naming
1475 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1476 // and because of that it doesn't follow the naming convention of the
1477 // rest of the file. To avoid a mixture of old vs new style, the new
1478 // style was chosen.
1479 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1480 dag OutOperandList = (outs);
1481 dag InOperandList = (ins GPROpnd:$rs);
1482 string AsmString = !strconcat(instr_asm, "\t$rs");
1483 list<dag> Pattern = [];
1486 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1487 dag OutOperandList = (outs GPROpnd:$rd);
1488 dag InOperandList = (ins GPROpnd:$rs);
1489 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1490 list<dag> Pattern = [];
1493 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1494 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1496 let isIndirectBranch=1;
1502 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1503 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1504 let isIndirectBranch=1;
1508 class JR_HB_ENC : JR_HB_FM<8>;
1509 class JALR_HB_ENC : JALR_HB_FM<9>;
1511 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1512 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1514 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1516 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1517 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1518 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1519 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1521 class CacheOp<string instr_asm, Operand MemOpnd> :
1522 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1523 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther> {
1524 let DecoderMethod = "DecodeCacheOp";
1527 def CACHE : CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1528 INSN_MIPS3_32_NOT_32R6_64R6;
1529 def PREF : CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1530 INSN_MIPS3_32_NOT_32R6_64R6;
1532 //===----------------------------------------------------------------------===//
1533 // Instruction aliases
1534 //===----------------------------------------------------------------------===//
1535 def : MipsInstAlias<"move $dst, $src",
1536 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1538 let AdditionalPredicates = [NotInMicroMips];
1540 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1541 ISA_MIPS1_NOT_32R6_64R6;
1542 def : MipsInstAlias<"addu $rs, $rt, $imm",
1543 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1544 def : MipsInstAlias<"addu $rs, $imm",
1545 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1546 def : MipsInstAlias<"add $rs, $rt, $imm",
1547 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1548 ISA_MIPS1_NOT_32R6_64R6;
1549 def : MipsInstAlias<"add $rs, $imm",
1550 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1551 ISA_MIPS1_NOT_32R6_64R6;
1552 def : MipsInstAlias<"and $rs, $rt, $imm",
1553 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1554 def : MipsInstAlias<"and $rs, $imm",
1555 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1556 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1557 let Predicates = [NotInMicroMips] in {
1558 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1560 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1561 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1562 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1563 def : MipsInstAlias<"not $rt, $rs",
1564 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1565 def : MipsInstAlias<"neg $rt, $rs",
1566 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1567 def : MipsInstAlias<"negu $rt",
1568 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1569 def : MipsInstAlias<"negu $rt, $rs",
1570 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1571 def : MipsInstAlias<"slt $rs, $rt, $imm",
1572 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1573 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1574 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1575 def : MipsInstAlias<"xor $rs, $rt, $imm",
1576 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1577 def : MipsInstAlias<"or $rs, $rt, $imm",
1578 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1579 def : MipsInstAlias<"or $rs, $imm",
1580 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1581 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1582 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1583 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1584 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1585 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1586 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1587 def : MipsInstAlias<"bnez $rs,$offset",
1588 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1589 def : MipsInstAlias<"beqz $rs,$offset",
1590 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1591 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1593 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1594 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1595 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1596 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1598 def : MipsInstAlias<"teq $rs, $rt",
1599 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1600 def : MipsInstAlias<"tge $rs, $rt",
1601 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1602 def : MipsInstAlias<"tgeu $rs, $rt",
1603 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1604 def : MipsInstAlias<"tlt $rs, $rt",
1605 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1606 def : MipsInstAlias<"tltu $rs, $rt",
1607 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1608 def : MipsInstAlias<"tne $rs, $rt",
1609 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1611 def : MipsInstAlias<"sll $rd, $rt, $rs",
1612 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1613 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1614 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1615 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1616 def : MipsInstAlias<"sub $rs, $imm",
1617 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1618 0>, ISA_MIPS1_NOT_32R6_64R6;
1619 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1620 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1621 InvertedImOperand:$imm), 0>;
1622 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1623 InvertedImOperand:$imm), 0>;
1624 def : MipsInstAlias<"sra $rd, $rt, $rs",
1625 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1626 def : MipsInstAlias<"srl $rd, $rt, $rs",
1627 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1628 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1629 def : MipsInstAlias<"sync",
1630 (SYNC 0), 1>, ISA_MIPS2;
1631 //===----------------------------------------------------------------------===//
1632 // Assembler Pseudo Instructions
1633 //===----------------------------------------------------------------------===//
1635 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1636 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1637 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1638 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1640 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1641 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1642 !strconcat(instr_asm, "\t$rt, $addr")> ;
1643 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1645 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1646 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1647 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1648 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1650 //===----------------------------------------------------------------------===//
1651 // Arbitrary patterns that map to one or more instructions
1652 //===----------------------------------------------------------------------===//
1654 // Load/store pattern templates.
1655 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1656 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1658 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1659 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1662 let AdditionalPredicates = [NotInMicroMips] in {
1663 def : MipsPat<(i32 immSExt16:$in),
1664 (ADDiu ZERO, imm:$in)>;
1665 def : MipsPat<(i32 immZExt16:$in),
1666 (ORi ZERO, imm:$in)>;
1668 def : MipsPat<(i32 immLow16Zero:$in),
1669 (LUi (HI16 imm:$in))>;
1671 // Arbitrary immediates
1672 def : MipsPat<(i32 imm:$imm),
1673 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1675 // Carry MipsPatterns
1676 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1677 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1678 let AdditionalPredicates = [NotDSP] in {
1679 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1680 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1681 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1682 (ADDiu GPR32:$src, imm:$imm)>;
1685 // Support multiplication for pre-Mips32 targets that don't have
1686 // the MUL instruction.
1687 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1688 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1689 ISA_MIPS1_NOT_32R6_64R6;
1692 def : MipsPat<(MipsSync (i32 immz)),
1693 (SYNC 0)>, ISA_MIPS2;
1696 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1697 (JAL tglobaladdr:$dst)>;
1698 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1699 (JAL texternalsym:$dst)>;
1700 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1701 // (JALR GPR32:$dst)>;
1704 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1705 (TAILCALL tglobaladdr:$dst)>;
1706 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1707 (TAILCALL texternalsym:$dst)>;
1709 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1710 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1711 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1712 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1713 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1714 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1716 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1717 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1718 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1719 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1720 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1721 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1723 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1724 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1725 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1726 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1727 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1728 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1729 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1730 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1731 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1732 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1735 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1736 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1737 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1738 (ADDiu GPR32:$gp, tconstpool:$in)>;
1741 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1742 MipsPat<(MipsWrapper RC:$gp, node:$in),
1743 (ADDiuOp RC:$gp, node:$in)>;
1745 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1746 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1747 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1748 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1749 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1750 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1752 // Mips does not have "not", so we expand our way
1753 def : MipsPat<(not GPR32:$in),
1754 (NOR GPR32Opnd:$in, ZERO)>;
1757 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1758 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1759 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1762 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1765 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1766 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1767 Instruction SLTiuOp, Register ZEROReg> {
1768 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1769 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1770 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1771 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1773 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1774 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1775 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1776 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1777 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1778 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1779 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1780 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1781 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1782 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1783 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1784 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1786 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1787 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1788 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1789 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1791 def : MipsPat<(brcond RC:$cond, bb:$dst),
1792 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1795 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1797 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1798 (BLEZ i32:$lhs, bb:$dst)>;
1799 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1800 (BGEZ i32:$lhs, bb:$dst)>;
1803 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1804 Instruction SLTuOp, Register ZEROReg> {
1805 def : MipsPat<(seteq RC:$lhs, 0),
1806 (SLTiuOp RC:$lhs, 1)>;
1807 def : MipsPat<(setne RC:$lhs, 0),
1808 (SLTuOp ZEROReg, RC:$lhs)>;
1809 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1810 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1811 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1812 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1815 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1816 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1817 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1818 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1819 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1822 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1823 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1824 (SLTOp RC:$rhs, RC:$lhs)>;
1825 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1826 (SLTuOp RC:$rhs, RC:$lhs)>;
1829 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1830 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1831 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1832 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1833 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1836 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1837 Instruction SLTiuOp> {
1838 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1839 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1840 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1841 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1844 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1845 defm : SetlePats<GPR32, SLT, SLTu>;
1846 defm : SetgtPats<GPR32, SLT, SLTu>;
1847 defm : SetgePats<GPR32, SLT, SLTu>;
1848 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1851 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1853 // Load halfword/word patterns.
1854 let AddedComplexity = 40 in {
1855 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1856 def : LoadRegImmPat<LH, i32, sextloadi16>;
1857 def : LoadRegImmPat<LW, i32, load>;
1860 //===----------------------------------------------------------------------===//
1861 // Floating Point Support
1862 //===----------------------------------------------------------------------===//
1864 include "MipsInstrFPU.td"
1865 include "Mips64InstrInfo.td"
1866 include "MipsCondMov.td"
1868 include "Mips32r6InstrInfo.td"
1869 include "Mips64r6InstrInfo.td"
1874 include "Mips16InstrFormats.td"
1875 include "Mips16InstrInfo.td"
1878 include "MipsDSPInstrFormats.td"
1879 include "MipsDSPInstrInfo.td"
1882 include "MipsMSAInstrFormats.td"
1883 include "MipsMSAInstrInfo.td"
1886 include "MicroMipsInstrFormats.td"
1887 include "MicroMipsInstrInfo.td"
1888 include "MicroMipsInstrFPU.td"