1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
240 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
241 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
242 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
244 // The portions of MIPS-III that were also added to MIPS32
245 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
247 // The portions of MIPS-III that were also added to MIPS32
248 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
250 // The portions of MIPS-IV that were also added to MIPS32
251 class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
253 // The portions of MIPS-IV that were also added to MIPS32R2
254 class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
256 // The portions of MIPS-V that were also added to MIPS32R2
257 class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; }
259 //===----------------------------------------------------------------------===//
261 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
262 let EncodingPredicates = [HasStdEnc];
265 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
266 InstAlias<Asm, Result, Emit>, PredicateControl;
269 bit isCommutable = 1;
286 bit isTerminator = 1;
289 bit hasExtraSrcRegAllocReq = 1;
290 bit isCodeGenOnly = 1;
293 class IsAsCheapAsAMove {
294 bit isAsCheapAsAMove = 1;
297 class NeverHasSideEffects {
298 bit neverHasSideEffects = 1;
301 //===----------------------------------------------------------------------===//
302 // Instruction format superclass
303 //===----------------------------------------------------------------------===//
305 include "MipsInstrFormats.td"
307 //===----------------------------------------------------------------------===//
308 // Mips Operand, Complex Patterns and Transformations Definitions.
309 //===----------------------------------------------------------------------===//
311 def MipsJumpTargetAsmOperand : AsmOperandClass {
312 let Name = "JumpTarget";
313 let ParserMethod = "ParseJumpTarget";
314 let PredicateMethod = "isImm";
315 let RenderMethod = "addImmOperands";
318 // Instruction operand types
319 def jmptarget : Operand<OtherVT> {
320 let EncoderMethod = "getJumpTargetOpValue";
321 let ParserMatchClass = MipsJumpTargetAsmOperand;
323 def brtarget : Operand<OtherVT> {
324 let EncoderMethod = "getBranchTargetOpValue";
325 let OperandType = "OPERAND_PCREL";
326 let DecoderMethod = "DecodeBranchTarget";
327 let ParserMatchClass = MipsJumpTargetAsmOperand;
329 def calltarget : Operand<iPTR> {
330 let EncoderMethod = "getJumpTargetOpValue";
331 let ParserMatchClass = MipsJumpTargetAsmOperand;
334 def simm10 : Operand<i32>;
336 def simm16 : Operand<i32> {
337 let DecoderMethod= "DecodeSimm16";
340 def simm19_lsl2 : Operand<i32> {
341 let EncoderMethod = "getSimm19Lsl2Encoding";
342 let DecoderMethod = "DecodeSimm19Lsl2";
345 def simm18_lsl3 : Operand<i32> {
346 let EncoderMethod = "getSimm18Lsl3Encoding";
347 let DecoderMethod = "DecodeSimm18Lsl3";
350 def simm20 : Operand<i32> {
353 def uimm20 : Operand<i32> {
356 def uimm10 : Operand<i32> {
359 def simm16_64 : Operand<i64> {
360 let DecoderMethod = "DecodeSimm16";
364 def uimmz : Operand<i32> {
365 let PrintMethod = "printUnsignedImm";
369 def uimm2 : Operand<i32> {
370 let PrintMethod = "printUnsignedImm";
373 def uimm3 : Operand<i32> {
374 let PrintMethod = "printUnsignedImm";
377 def uimm5 : Operand<i32> {
378 let PrintMethod = "printUnsignedImm";
381 def uimm6 : Operand<i32> {
382 let PrintMethod = "printUnsignedImm";
385 def uimm16 : Operand<i32> {
386 let PrintMethod = "printUnsignedImm";
389 def pcrel16 : Operand<i32> {
392 def MipsMemAsmOperand : AsmOperandClass {
394 let ParserMethod = "parseMemOperand";
397 def MipsInvertedImmoperand : AsmOperandClass {
399 let RenderMethod = "addImmOperands";
400 let ParserMethod = "parseInvNum";
403 def InvertedImOperand : Operand<i32> {
404 let ParserMatchClass = MipsInvertedImmoperand;
407 def InvertedImOperand64 : Operand<i64> {
408 let ParserMatchClass = MipsInvertedImmoperand;
411 class mem_generic : Operand<iPTR> {
412 let PrintMethod = "printMemOperand";
413 let MIOperandInfo = (ops ptr_rc, simm16);
414 let EncoderMethod = "getMemEncoding";
415 let ParserMatchClass = MipsMemAsmOperand;
416 let OperandType = "OPERAND_MEMORY";
420 def mem : mem_generic;
422 // MSA specific address operand
423 def mem_msa : mem_generic {
424 let MIOperandInfo = (ops ptr_rc, simm10);
425 let EncoderMethod = "getMSAMemEncoding";
428 def mem_ea : Operand<iPTR> {
429 let PrintMethod = "printMemOperandEA";
430 let MIOperandInfo = (ops ptr_rc, simm16);
431 let EncoderMethod = "getMemEncoding";
432 let OperandType = "OPERAND_MEMORY";
435 def PtrRC : Operand<iPTR> {
436 let MIOperandInfo = (ops ptr_rc);
437 let DecoderMethod = "DecodePtrRegisterClass";
438 let ParserMatchClass = GPR32AsmOperand;
441 // size operand of ext instruction
442 def size_ext : Operand<i32> {
443 let EncoderMethod = "getSizeExtEncoding";
444 let DecoderMethod = "DecodeExtSize";
447 // size operand of ins instruction
448 def size_ins : Operand<i32> {
449 let EncoderMethod = "getSizeInsEncoding";
450 let DecoderMethod = "DecodeInsSize";
453 // Transformation Function - get the lower 16 bits.
454 def LO16 : SDNodeXForm<imm, [{
455 return getImm(N, N->getZExtValue() & 0xFFFF);
458 // Transformation Function - get the higher 16 bits.
459 def HI16 : SDNodeXForm<imm, [{
460 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
464 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
466 // Node immediate is zero (e.g. insve.d)
467 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
469 // Node immediate fits as 16-bit sign extended on target immediate.
471 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
473 // Node immediate fits as 16-bit sign extended on target immediate.
475 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
477 // Node immediate fits as 15-bit sign extended on target immediate.
479 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
481 // Node immediate fits as 16-bit zero extended on target immediate.
482 // The LO16 param means that only the lower 16 bits of the node
483 // immediate are caught.
485 def immZExt16 : PatLeaf<(imm), [{
486 if (N->getValueType(0) == MVT::i32)
487 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
489 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
492 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
493 def immLow16Zero : PatLeaf<(imm), [{
494 int64_t Val = N->getSExtValue();
495 return isInt<32>(Val) && !(Val & 0xffff);
498 // shamt field must fit in 5 bits.
499 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
501 // True if (N + 1) fits in 16-bit field.
502 def immSExt16Plus1 : PatLeaf<(imm), [{
503 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
506 // Mips Address Mode! SDNode frameindex could possibily be a match
507 // since load and store instructions from stack used it.
509 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
512 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
515 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
518 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
520 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
522 //===----------------------------------------------------------------------===//
523 // Instructions specific format
524 //===----------------------------------------------------------------------===//
526 // Arithmetic and logical instructions with 3 register operands.
527 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
528 InstrItinClass Itin = NoItinerary,
529 SDPatternOperator OpNode = null_frag>:
530 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
531 !strconcat(opstr, "\t$rd, $rs, $rt"),
532 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
533 let isCommutable = isComm;
534 let isReMaterializable = 1;
535 let TwoOperandAliasConstraint = "$rd = $rs";
538 // Arithmetic and logical instructions with 2 register operands.
539 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
540 InstrItinClass Itin = NoItinerary,
541 SDPatternOperator imm_type = null_frag,
542 SDPatternOperator OpNode = null_frag> :
543 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
544 !strconcat(opstr, "\t$rt, $rs, $imm16"),
545 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
547 let isReMaterializable = 1;
548 let TwoOperandAliasConstraint = "$rs = $rt";
551 // Arithmetic Multiply ADD/SUB
552 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
553 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
554 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
555 let Defs = [HI0, LO0];
556 let Uses = [HI0, LO0];
557 let isCommutable = isComm;
561 class LogicNOR<string opstr, RegisterOperand RO>:
562 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
563 !strconcat(opstr, "\t$rd, $rs, $rt"),
564 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
565 let isCommutable = 1;
569 class shift_rotate_imm<string opstr, Operand ImmOpnd,
570 RegisterOperand RO, InstrItinClass itin,
571 SDPatternOperator OpNode = null_frag,
572 SDPatternOperator PF = null_frag> :
573 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
574 !strconcat(opstr, "\t$rd, $rt, $shamt"),
575 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
576 let TwoOperandAliasConstraint = "$rt = $rd";
579 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
580 SDPatternOperator OpNode = null_frag>:
581 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
582 !strconcat(opstr, "\t$rd, $rt, $rs"),
583 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
586 // Load Upper Imediate
587 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
588 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
589 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
590 let neverHasSideEffects = 1;
591 let isReMaterializable = 1;
595 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
596 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
597 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
598 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
599 let DecoderMethod = "DecodeMem";
600 let canFoldAsLoad = 1;
604 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
605 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
606 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
607 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
608 let DecoderMethod = "DecodeMem";
612 // Load/Store Left/Right
613 let canFoldAsLoad = 1 in
614 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
615 InstrItinClass Itin> :
616 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
617 !strconcat(opstr, "\t$rt, $addr"),
618 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
619 let DecoderMethod = "DecodeMem";
620 string Constraints = "$src = $rt";
623 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
624 InstrItinClass Itin> :
625 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
626 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
627 let DecoderMethod = "DecodeMem";
630 // Conditional Branch
631 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
632 RegisterOperand RO> :
633 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
634 !strconcat(opstr, "\t$rs, $rt, $offset"),
635 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
638 let isTerminator = 1;
639 let hasDelaySlot = 1;
643 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
644 RegisterOperand RO> :
645 InstSE<(outs), (ins RO:$rs, opnd:$offset),
646 !strconcat(opstr, "\t$rs, $offset"),
647 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
650 let isTerminator = 1;
651 let hasDelaySlot = 1;
656 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
657 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
658 !strconcat(opstr, "\t$rd, $rs, $rt"),
659 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
660 II_SLT_SLTU, FrmR, opstr>;
662 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
664 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
665 !strconcat(opstr, "\t$rt, $rs, $imm16"),
666 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
667 II_SLTI_SLTIU, FrmI, opstr>;
670 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
671 SDPatternOperator targetoperator, string bopstr> :
672 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
673 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
676 let hasDelaySlot = 1;
677 let DecoderMethod = "DecodeJumpTarget";
681 // Unconditional branch
682 class UncondBranch<Instruction BEQInst> :
683 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
684 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
686 let isTerminator = 1;
688 let hasDelaySlot = 1;
689 let AdditionalPredicates = [RelocPIC];
693 // Base class for indirect branch and return instruction classes.
694 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
695 class JumpFR<string opstr, RegisterOperand RO,
696 SDPatternOperator operator = null_frag>:
697 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
701 class IndirectBranch<string opstr, RegisterOperand RO> :
702 JumpFR<opstr, RO, brind> {
704 let isIndirectBranch = 1;
707 // Return instruction
708 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
710 let isCodeGenOnly = 1;
712 let hasExtraSrcRegAllocReq = 1;
715 // Jump and Link (Call)
716 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
717 class JumpLink<string opstr, DAGOperand opnd> :
718 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
719 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
720 let DecoderMethod = "DecodeJumpTarget";
723 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
724 Register RetReg, RegisterOperand ResRO = RO>:
725 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
726 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
728 class JumpLinkReg<string opstr, RegisterOperand RO>:
729 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
732 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
733 InstSE<(outs), (ins RO:$rs, opnd:$offset),
734 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
738 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
739 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
740 class TailCall<Instruction JumpInst> :
741 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
742 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
744 class TailCallReg<RegisterOperand RO, Instruction JRInst,
745 RegisterOperand ResRO = RO> :
746 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
747 PseudoInstExpansion<(JRInst ResRO:$rs)>;
750 class BAL_BR_Pseudo<Instruction RealInst> :
751 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
752 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
754 let isTerminator = 1;
756 let hasDelaySlot = 1;
761 class SYS_FT<string opstr> :
762 InstSE<(outs), (ins uimm20:$code_),
763 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
765 class BRK_FT<string opstr> :
766 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
767 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
771 class ER_FT<string opstr> :
772 InstSE<(outs), (ins),
773 opstr, [], NoItinerary, FrmOther, opstr>;
776 class DEI_FT<string opstr, RegisterOperand RO> :
777 InstSE<(outs RO:$rt), (ins),
778 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
781 class WAIT_FT<string opstr> :
782 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
785 let hasSideEffects = 1 in
786 class SYNC_FT<string opstr> :
787 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
788 NoItinerary, FrmOther, opstr>;
790 let hasSideEffects = 1 in
791 class TEQ_FT<string opstr, RegisterOperand RO> :
792 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
793 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
796 class TEQI_FT<string opstr, RegisterOperand RO> :
797 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
798 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
800 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
801 list<Register> DefRegs> :
802 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
804 let isCommutable = 1;
806 let neverHasSideEffects = 1;
809 // Pseudo multiply/divide instruction with explicit accumulator register
811 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
812 SDPatternOperator OpNode, InstrItinClass Itin,
813 bit IsComm = 1, bit HasSideEffects = 0,
814 bit UsesCustomInserter = 0> :
815 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
816 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
817 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
818 let isCommutable = IsComm;
819 let hasSideEffects = HasSideEffects;
820 let usesCustomInserter = UsesCustomInserter;
823 // Pseudo multiply add/sub instruction with explicit accumulator register
825 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
827 : PseudoSE<(outs ACC64:$ac),
828 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
830 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
832 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
833 string Constraints = "$acin = $ac";
836 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
837 list<Register> DefRegs> :
838 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
839 [], itin, FrmR, opstr> {
844 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
845 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
846 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
848 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
849 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
852 let neverHasSideEffects = 1;
855 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
856 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
857 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
860 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
861 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
864 let neverHasSideEffects = 1;
867 class EffectiveAddress<string opstr, RegisterOperand RO> :
868 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
869 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
870 !strconcat(opstr, "_lea")> {
871 let isCodeGenOnly = 1;
872 let DecoderMethod = "DecodeMem";
875 // Count Leading Ones/Zeros in Word
876 class CountLeading0<string opstr, RegisterOperand RO>:
877 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
878 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
880 class CountLeading1<string opstr, RegisterOperand RO>:
881 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
882 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
884 // Sign Extend in Register.
885 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
886 InstrItinClass itin> :
887 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
888 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
891 class SubwordSwap<string opstr, RegisterOperand RO>:
892 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
893 NoItinerary, FrmR, opstr> {
894 let neverHasSideEffects = 1;
898 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
899 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
903 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
904 SDPatternOperator Op = null_frag>:
905 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
906 !strconcat(opstr, " $rt, $rs, $pos, $size"),
907 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
908 FrmR, opstr>, ISA_MIPS32R2;
910 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
911 SDPatternOperator Op = null_frag>:
912 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
913 !strconcat(opstr, " $rt, $rs, $pos, $size"),
914 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
915 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
916 let Constraints = "$src = $rt";
919 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
920 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
921 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
922 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
924 // Atomic Compare & Swap.
925 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
926 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
927 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
929 class LLBase<string opstr, RegisterOperand RO> :
930 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
931 [], NoItinerary, FrmI> {
932 let DecoderMethod = "DecodeMem";
936 class SCBase<string opstr, RegisterOperand RO> :
937 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
938 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
939 let DecoderMethod = "DecodeMem";
941 let Constraints = "$rt = $dst";
944 class MFC3OP<string asmstr, RegisterOperand RO> :
945 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
946 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
948 class TrapBase<Instruction RealInst>
949 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
950 PseudoInstExpansion<(RealInst 0, 0)> {
952 let isTerminator = 1;
953 let isCodeGenOnly = 1;
956 //===----------------------------------------------------------------------===//
957 // Pseudo instructions
958 //===----------------------------------------------------------------------===//
961 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
962 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
964 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
965 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
966 [(callseq_start timm:$amt)]>;
967 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
968 [(callseq_end timm:$amt1, timm:$amt2)]>;
971 let usesCustomInserter = 1 in {
972 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
973 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
974 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
975 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
976 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
977 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
978 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
979 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
980 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
981 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
982 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
983 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
984 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
985 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
986 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
987 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
988 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
989 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
991 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
992 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
993 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
995 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
996 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
997 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1000 /// Pseudo instructions for loading and storing accumulator registers.
1001 let isPseudo = 1, isCodeGenOnly = 1 in {
1002 def LOAD_ACC64 : Load<"", ACC64>;
1003 def STORE_ACC64 : Store<"", ACC64>;
1006 // We need these two pseudo instructions to avoid offset calculation for long
1007 // branches. See the comment in file MipsLongBranch.cpp for detailed
1010 // Expands to: lui $dst, %hi($tgt - $baltgt)
1011 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1012 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1014 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1015 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1016 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1018 //===----------------------------------------------------------------------===//
1019 // Instruction definition
1020 //===----------------------------------------------------------------------===//
1021 //===----------------------------------------------------------------------===//
1022 // MipsI Instructions
1023 //===----------------------------------------------------------------------===//
1025 /// Arithmetic Instructions (ALU Immediate)
1026 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1028 ADDI_FM<0x9>, IsAsCheapAsAMove;
1029 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1030 ISA_MIPS1_NOT_32R6_64R6;
1031 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1033 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1035 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1038 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1041 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1044 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1046 /// Arithmetic Instructions (3-Operand, R-Type)
1047 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1049 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1051 let Defs = [HI0, LO0] in
1052 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1053 ADD_FM<0x1c, 2>, ISA_MIPS32;
1054 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1055 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1056 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1057 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1058 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1060 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1062 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1064 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1066 /// Shift Instructions
1067 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1068 immZExt5>, SRA_FM<0, 0>;
1069 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1070 immZExt5>, SRA_FM<2, 0>;
1071 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1072 immZExt5>, SRA_FM<3, 0>;
1073 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1075 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1077 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1080 // Rotate Instructions
1081 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1083 SRA_FM<2, 1>, ISA_MIPS32R2;
1084 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1085 SRLV_FM<6, 1>, ISA_MIPS32R2;
1087 /// Load and Store Instructions
1089 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1090 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1092 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1094 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1095 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1097 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1098 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1099 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1101 /// load/store left/right
1102 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1103 AdditionalPredicates = [NotInMicroMips] in {
1104 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1105 ISA_MIPS1_NOT_32R6_64R6;
1106 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1107 ISA_MIPS1_NOT_32R6_64R6;
1108 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1109 ISA_MIPS1_NOT_32R6_64R6;
1110 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1111 ISA_MIPS1_NOT_32R6_64R6;
1114 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1115 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1116 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1117 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1118 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1119 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1120 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1122 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1123 ISA_MIPS2_NOT_32R6_64R6;
1124 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1125 ISA_MIPS2_NOT_32R6_64R6;
1126 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1127 ISA_MIPS2_NOT_32R6_64R6;
1128 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1129 ISA_MIPS2_NOT_32R6_64R6;
1130 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1131 ISA_MIPS2_NOT_32R6_64R6;
1132 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1133 ISA_MIPS2_NOT_32R6_64R6;
1135 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1136 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1137 def TRAP : TrapBase<BREAK>;
1139 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1140 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1142 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1143 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1145 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1146 AdditionalPredicates = [NotInMicroMips] in {
1147 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1149 /// Load-linked, Store-conditional
1150 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1151 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1154 /// Jump and Branch Instructions
1155 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1156 AdditionalRequires<[RelocStatic]>, IsBranch;
1157 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1158 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1159 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1160 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1162 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1164 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1166 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1168 def B : UncondBranch<BEQ>;
1170 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1171 let AdditionalPredicates = [NotInMicroMips] in {
1172 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1173 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1175 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1176 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1177 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1178 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1179 def TAILCALL : TailCall<J>;
1180 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1182 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1184 // Exception handling related node and instructions.
1185 // The conversion sequence is:
1186 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1187 // MIPSeh_return -> (stack change + indirect branch)
1189 // MIPSeh_return takes the place of regular return instruction
1190 // but takes two arguments (V1, V0) which are used for storing
1191 // the offset and return address respectively.
1192 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1194 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1195 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1197 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1198 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1199 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1200 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1202 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1205 /// Multiply and Divide Instructions.
1206 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1208 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1210 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1212 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1215 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1216 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1217 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1218 AdditionalPredicates = [NotInMicroMips] in {
1219 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1220 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1223 /// Sign Ext In Register Instructions.
1224 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1225 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1226 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1227 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1230 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1231 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1233 /// Word Swap Bytes Within Halfwords
1234 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1237 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1239 // FrameIndexes are legalized when they are operands from load/store
1240 // instructions. The same not happens for stack address copies, so an
1241 // add op with mem ComplexPattern is used and the stack address copy
1242 // can be matched. It's similar to Sparc LEA_ADDRi
1243 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1246 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, ISA_MIPS32;
1247 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, ISA_MIPS32;
1248 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, ISA_MIPS32;
1249 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, ISA_MIPS32;
1251 let AdditionalPredicates = [NotDSP] in {
1252 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1253 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1254 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1255 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1256 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1257 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1258 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1259 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1260 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1263 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1265 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1268 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1270 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1271 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1273 /// Move Control Registers From/To CPU Registers
1274 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1275 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1276 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1277 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1279 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1281 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1282 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1283 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1285 // JR_HB and JALR_HB are defined here using the new style naming
1286 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1287 // and because of that it doesn't follow the naming convention of the
1288 // rest of the file. To avoid a mixture of old vs new style, the new
1289 // style was chosen.
1290 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1291 dag OutOperandList = (outs);
1292 dag InOperandList = (ins GPROpnd:$rs);
1293 string AsmString = !strconcat(instr_asm, "\t$rs");
1294 list<dag> Pattern = [];
1297 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1298 dag OutOperandList = (outs GPROpnd:$rd);
1299 dag InOperandList = (ins GPROpnd:$rs);
1300 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1301 list<dag> Pattern = [];
1304 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1305 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1307 let isIndirectBranch=1;
1313 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1314 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1315 let isIndirectBranch=1;
1319 class JR_HB_ENC : JR_HB_FM<8>;
1320 class JALR_HB_ENC : JALR_HB_FM<9>;
1322 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1323 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1325 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1327 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1328 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1329 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1330 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1332 //===----------------------------------------------------------------------===//
1333 // Instruction aliases
1334 //===----------------------------------------------------------------------===//
1335 def : MipsInstAlias<"move $dst, $src",
1336 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1338 let AdditionalPredicates = [NotInMicroMips];
1340 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1341 def : MipsInstAlias<"addu $rs, $rt, $imm",
1342 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1343 def : MipsInstAlias<"add $rs, $rt, $imm",
1344 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1345 def : MipsInstAlias<"and $rs, $rt, $imm",
1346 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1347 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1348 let Predicates = [NotInMicroMips] in {
1349 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1351 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1352 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1353 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1354 def : MipsInstAlias<"not $rt, $rs",
1355 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1356 def : MipsInstAlias<"neg $rt, $rs",
1357 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1358 def : MipsInstAlias<"negu $rt",
1359 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1360 def : MipsInstAlias<"negu $rt, $rs",
1361 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1362 def : MipsInstAlias<"slt $rs, $rt, $imm",
1363 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1364 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1365 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1366 def : MipsInstAlias<"xor $rs, $rt, $imm",
1367 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1368 def : MipsInstAlias<"or $rs, $rt, $imm",
1369 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1370 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1371 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1372 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1373 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1374 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1375 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1376 def : MipsInstAlias<"bnez $rs,$offset",
1377 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1378 def : MipsInstAlias<"beqz $rs,$offset",
1379 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1380 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1382 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1383 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1384 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1385 def : MipsInstAlias<"di", (DI ZERO), 1>;
1387 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1388 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1389 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1391 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1392 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1394 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1395 def : MipsInstAlias<"sll $rd, $rt, $rs",
1396 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1397 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1398 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1399 InvertedImOperand:$imm), 0>;
1400 def : MipsInstAlias<"sub $rs, $imm",
1401 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1403 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1404 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1405 InvertedImOperand:$imm), 0>;
1406 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1407 InvertedImOperand:$imm), 0>;
1408 def : MipsInstAlias<"sra $rd, $rt, $rs",
1409 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1410 def : MipsInstAlias<"srl $rd, $rt, $rs",
1411 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1412 //===----------------------------------------------------------------------===//
1413 // Assembler Pseudo Instructions
1414 //===----------------------------------------------------------------------===//
1416 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1417 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1418 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1419 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1421 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1422 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1423 !strconcat(instr_asm, "\t$rt, $addr")> ;
1424 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1426 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1427 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1428 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1429 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1431 //===----------------------------------------------------------------------===//
1432 // Arbitrary patterns that map to one or more instructions
1433 //===----------------------------------------------------------------------===//
1435 // Load/store pattern templates.
1436 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1437 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1439 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1440 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1443 def : MipsPat<(i32 immSExt16:$in),
1444 (ADDiu ZERO, imm:$in)>;
1445 def : MipsPat<(i32 immZExt16:$in),
1446 (ORi ZERO, imm:$in)>;
1447 def : MipsPat<(i32 immLow16Zero:$in),
1448 (LUi (HI16 imm:$in))>;
1450 // Arbitrary immediates
1451 def : MipsPat<(i32 imm:$imm),
1452 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1454 // Carry MipsPatterns
1455 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1456 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1457 let AdditionalPredicates = [NotDSP] in {
1458 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1459 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1460 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1461 (ADDiu GPR32:$src, imm:$imm)>;
1465 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1466 (JAL tglobaladdr:$dst)>;
1467 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1468 (JAL texternalsym:$dst)>;
1469 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1470 // (JALR GPR32:$dst)>;
1473 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1474 (TAILCALL tglobaladdr:$dst)>;
1475 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1476 (TAILCALL texternalsym:$dst)>;
1478 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1479 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1480 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1481 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1482 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1483 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1485 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1486 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1487 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1488 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1489 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1490 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1492 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1493 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1494 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1495 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1496 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1497 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1498 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1499 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1500 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1501 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1504 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1505 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1506 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1507 (ADDiu GPR32:$gp, tconstpool:$in)>;
1510 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1511 MipsPat<(MipsWrapper RC:$gp, node:$in),
1512 (ADDiuOp RC:$gp, node:$in)>;
1514 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1515 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1516 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1517 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1518 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1519 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1521 // Mips does not have "not", so we expand our way
1522 def : MipsPat<(not GPR32:$in),
1523 (NOR GPR32Opnd:$in, ZERO)>;
1526 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1527 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1528 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1531 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1534 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1535 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1536 Instruction SLTiuOp, Register ZEROReg> {
1537 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1538 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1539 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1540 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1542 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1543 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1544 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1545 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1546 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1547 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1548 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1549 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1550 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1551 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1552 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1553 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1555 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1556 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1557 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1558 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1560 def : MipsPat<(brcond RC:$cond, bb:$dst),
1561 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1564 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1566 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1567 (BLEZ i32:$lhs, bb:$dst)>;
1568 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1569 (BGEZ i32:$lhs, bb:$dst)>;
1572 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1573 Instruction SLTuOp, Register ZEROReg> {
1574 def : MipsPat<(seteq RC:$lhs, 0),
1575 (SLTiuOp RC:$lhs, 1)>;
1576 def : MipsPat<(setne RC:$lhs, 0),
1577 (SLTuOp ZEROReg, RC:$lhs)>;
1578 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1579 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1580 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1581 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1584 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1585 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1586 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1587 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1588 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1591 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1592 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1593 (SLTOp RC:$rhs, RC:$lhs)>;
1594 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1595 (SLTuOp RC:$rhs, RC:$lhs)>;
1598 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1599 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1600 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1601 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1602 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1605 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1606 Instruction SLTiuOp> {
1607 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1608 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1609 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1610 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1613 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1614 defm : SetlePats<GPR32, SLT, SLTu>;
1615 defm : SetgtPats<GPR32, SLT, SLTu>;
1616 defm : SetgePats<GPR32, SLT, SLTu>;
1617 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1620 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1622 // Load halfword/word patterns.
1623 let AddedComplexity = 40 in {
1624 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1625 def : LoadRegImmPat<LH, i32, sextloadi16>;
1626 def : LoadRegImmPat<LW, i32, load>;
1629 //===----------------------------------------------------------------------===//
1630 // Floating Point Support
1631 //===----------------------------------------------------------------------===//
1633 include "MipsInstrFPU.td"
1634 include "Mips64InstrInfo.td"
1635 include "MipsCondMov.td"
1637 include "Mips32r6InstrInfo.td"
1638 include "Mips64r6InstrInfo.td"
1643 include "Mips16InstrFormats.td"
1644 include "Mips16InstrInfo.td"
1647 include "MipsDSPInstrFormats.td"
1648 include "MipsDSPInstrInfo.td"
1651 include "MipsMSAInstrFormats.td"
1652 include "MipsMSAInstrInfo.td"
1655 include "MicroMipsInstrFormats.td"
1656 include "MicroMipsInstrInfo.td"
1657 include "MicroMipsInstrFPU.td"